From patchwork Fri Dec 17 23:50:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 76036 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2F45FB6F07 for ; Sat, 18 Dec 2010 10:53:16 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E369828223; Sat, 18 Dec 2010 00:52:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9nkTENjYG6l5; Sat, 18 Dec 2010 00:52:20 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 275552822B; Sat, 18 Dec 2010 00:51:42 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E8D83281BF for ; Sat, 18 Dec 2010 00:51:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LkgulUZnIz8t for ; Sat, 18 Dec 2010 00:51:39 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id C5D7E281BD for ; Sat, 18 Dec 2010 00:51:11 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id oBHNp9lm012800 for ; Fri, 17 Dec 2010 17:51:09 -0600 From: Kumar Gala To: u-boot@lists.denx.de Date: Fri, 17 Dec 2010 17:50:55 -0600 Message-Id: <1292629858-10233-12-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <1292629858-10233-11-git-send-email-galak@kernel.crashing.org> References: <1292629858-10233-1-git-send-email-galak@kernel.crashing.org> <1292629858-10233-2-git-send-email-galak@kernel.crashing.org> <1292629858-10233-3-git-send-email-galak@kernel.crashing.org> <1292629858-10233-4-git-send-email-galak@kernel.crashing.org> <1292629858-10233-5-git-send-email-galak@kernel.crashing.org> <1292629858-10233-6-git-send-email-galak@kernel.crashing.org> <1292629858-10233-7-git-send-email-galak@kernel.crashing.org> <1292629858-10233-8-git-send-email-galak@kernel.crashing.org> <1292629858-10233-9-git-send-email-galak@kernel.crashing.org> <1292629858-10233-10-git-send-email-galak@kernel.crashing.org> <1292629858-10233-11-git-send-email-galak@kernel.crashing.org> Subject: [U-Boot] [PATCH 12/15] powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Remove duplicated code in P1_P2_RDB boards and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/law.c | 6 +--- board/freescale/p1_p2_rdb/pci.c | 64 +++++--------------------------------- 2 files changed, 10 insertions(+), 60 deletions(-) diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c index 1320d5d..4c80fa6 100644 --- a/board/freescale/p1_p2_rdb/law.c +++ b/board/freescale/p1_p2_rdb/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -26,10 +26,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 2034459..ccfc996 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -32,65 +32,19 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif +static const char *slot_names[] = { + [PCIE1] = "Slot 2", + [PCIE2] = "Slot 1", +}; -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif +const char *board_serdes_name(enum srds_prtcl device) +{ + return slot_names[device]; +} void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[2]; - u32 devdisr, pordevsr; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - - puts("\n"); -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif + fsl_pcie_init_board(0); } void ft_pci_board_setup(void *blob)