Patchwork [ARM] Don't generate redundant zero_extend before smlabb

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Submitter Andrew Stubbs
Date Dec. 17, 2010, 4:31 p.m.
Message ID <4D0B905E.1040705@codesourcery.com>
Download mbox | patch
Permalink /patch/75922/
State New
Headers show

Comments

Andrew Stubbs - Dec. 17, 2010, 4:31 p.m.
On 16/12/10 18:26, Richard Earnshaw wrote:
> This is ok to go in now.  While you're modifying these patterns, the %
> in the register constraint does not do anything useful (and actually
> makes the compiler slightly slower) since the constraints and predicates
> are otherwise identical, so it might as well be removed.
>

Thanks Richard.

I've made the adjustment, and committed the attached.

Andrew

Patch

2010-12-17  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical
	operand order for plus.
	Drop redundant % from constraints.

---
 src/gcc-mainline/gcc/config/arm/arm.md |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gcc-mainline/gcc/config/arm/arm.md b/src/gcc-mainline/gcc/config/arm/arm.md
index 20431d3..dd7555b 100644
--- a/src/gcc-mainline/gcc/config/arm/arm.md
+++ b/src/gcc-mainline/gcc/config/arm/arm.md
@@ -1793,11 +1793,11 @@ 
 
 (define_insn "maddhisi4"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(plus:SI (match_operand:SI 3 "s_register_operand" "r")
-		 (mult:SI (sign_extend:SI
-			   (match_operand:HI 1 "s_register_operand" "%r"))
+	(plus:SI (mult:SI (sign_extend:SI
+			   (match_operand:HI 1 "s_register_operand" "r"))
 			  (sign_extend:SI
-			   (match_operand:HI 2 "s_register_operand" "r")))))]
+			   (match_operand:HI 2 "s_register_operand" "r")))
+		 (match_operand:SI 3 "s_register_operand" "r")))]
   "TARGET_DSP_MULTIPLY"
   "smlabb%?\\t%0, %1, %2, %3"
   [(set_attr "insn" "smlaxy")
@@ -1807,11 +1807,11 @@ 
 (define_insn "*maddhidi4"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
 	(plus:DI
-	  (match_operand:DI 3 "s_register_operand" "0")
 	  (mult:DI (sign_extend:DI
-	 	    (match_operand:HI 1 "s_register_operand" "%r"))
+	 	    (match_operand:HI 1 "s_register_operand" "r"))
 		   (sign_extend:DI
-		    (match_operand:HI 2 "s_register_operand" "r")))))]
+		    (match_operand:HI 2 "s_register_operand" "r")))
+	  (match_operand:DI 3 "s_register_operand" "0")))]
   "TARGET_DSP_MULTIPLY"
   "smlalbb%?\\t%Q0, %R0, %1, %2"
   [(set_attr "insn" "smlalxy")