From patchwork Thu Dec 16 22:45:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carrot Wei X-Patchwork-Id: 75815 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id F1D411007D3 for ; Fri, 17 Dec 2010 09:45:37 +1100 (EST) Received: (qmail 16022 invoked by alias); 16 Dec 2010 22:45:29 -0000 Received: (qmail 15921 invoked by uid 22791); 16 Dec 2010 22:45:27 -0000 X-SWARE-Spam-Status: No, hits=-5.1 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, SPF_HELO_PASS, TW_CN, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (74.125.121.35) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 16 Dec 2010 22:45:21 +0000 Received: from wpaz17.hot.corp.google.com (wpaz17.hot.corp.google.com [172.24.198.81]) by smtp-out.google.com with ESMTP id oBGMjIEH032378 for ; Thu, 16 Dec 2010 14:45:18 -0800 Received: from yxh35 (yxh35.prod.google.com [10.190.2.227]) by wpaz17.hot.corp.google.com with ESMTP id oBGMjHiI006245 for ; Thu, 16 Dec 2010 14:45:17 -0800 Received: by yxh35 with SMTP id 35so30207yxh.41 for ; Thu, 16 Dec 2010 14:45:17 -0800 (PST) MIME-Version: 1.0 Received: by 10.150.200.12 with SMTP id x12mr1754477ybf.134.1292539516991; Thu, 16 Dec 2010 14:45:16 -0800 (PST) Received: by 10.151.105.6 with HTTP; Thu, 16 Dec 2010 14:45:16 -0800 (PST) Date: Thu, 16 Dec 2010 14:45:16 -0800 Message-ID: Subject: [PATCH: PR target/46975] Replace 32 bit instructions with 16 bit instructions in thumb2 From: Carrot Wei To: gcc-patches@gcc.gnu.org X-System-Of-Record: true Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi Compile the following c code with options -march=armv7-a -mthumb -Os int foo (int s) { return s == 1; } GCC 4.6 generates: 00000000 : 0: f1a0 0301 sub.w r3, r0, #1 // A 4: 4258 negs r0, r3 6: eb40 0003 adc.w r0, r0, r3 // B a: 4770 bx lr Notice that instructions A and B are 32 bits. In thumb2 we can use subs and adcs instead so they will be 16 bits. The root cause is the following peephole2 generates 32 bit instructions: 8731 ;; Attempt to improve the sequence generated by the compare_scc splitters 8732 ;; not to use conditional execution. 8733 (define_peephole2 8734 [(set (reg:CC CC_REGNUM) 8735 (compare:CC (match_operand:SI 1 "register_operand" "") 8736 (match_operand:SI 2 "arm_rhs_operand" ""))) 8737 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) 8738 (set (match_operand:SI 0 "register_operand" "") (const_int 0))) 8739 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) 8740 (set (match_dup 0) (const_int 1))) 8741 (match_scratch:SI 3 "r")] 8742 "TARGET_32BIT" 8743 [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 8744 (parallel 8745 [(set (reg:CC CC_REGNUM) 8746 (compare:CC (const_int 0) (match_dup 3))) 8747 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) 8748 (set (match_dup 0) 8749 (plus:SI (plus:SI (match_dup 0) (match_dup 3)) 8750 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]) 8751 This patch modifies the peephole2 to generate 16 bit instructions, and passed regression test on arm qemu. thanks Guozhi ChangeLog: 2010-12-16 Wei Guozhi PR target/46975 * config/arm/arm.md (*addsi3_carryin_compare0_): New pattern. (peephole2 for conditional move): Generate 16 bit instructions. ChangeLog: 2010-12-16 Wei Guozhi PR target/46975 * gcc.target/arm/pr46975.c: New testcase. Index: arm.md =================================================================== --- arm.md (revision 167861) +++ arm.md (working copy) @@ -974,6 +974,21 @@ (const_string "alu_shift_reg")))] ) +(define_insn "*addsi3_carryin_compare0_" + [(set (reg:CC CC_REGNUM) + (compare:CC + (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") + (match_operand:SI 2 "arm_rhs_operand" "rI")) + (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (plus:SI (match_dup 1) (match_dup 2)) + (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "adc%.\\t%0, %1, %2" + [(set_attr "conds" "set")] + ) + (define_expand "incscc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_operator:SI 2 "arm_comparison_operator" @@ -8748,14 +8763,22 @@ (set (match_dup 0) (const_int 1))) (match_scratch:SI 3 "r")] "TARGET_32BIT" - [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) + [(parallel + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))]) (parallel [(set (reg:CC CC_REGNUM) (compare:CC (const_int 0) (match_dup 3))) (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) - (set (match_dup 0) - (plus:SI (plus:SI (match_dup 0) (match_dup 3)) - (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]) + (parallel + [(set (reg:CC CC_REGNUM) + (compare:CC (plus:SI (plus:SI (match_dup 0) (match_dup 3)) + (geu:SI (reg:CC CC_REGNUM) (const_int 0))) + (const_int 0))) + (set (match_dup 0) + (plus:SI (plus:SI (match_dup 0) (match_dup 3)) + (geu:SI (reg:CC CC_REGNUM) (const_int 0))))])]) (define_insn "*cond_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") Index: pr46975.c =================================================================== --- pr46975.c (revision 0) +++ pr46975.c (revision 0) @@ -0,0 +1,9 @@ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "subs" } } */ +/* { dg-final { scan-assembler "adcs" } } */ + +int foo (int s) +{ + return s == 1; +}