| Message ID | 1493713190-4505-2-git-send-email-eric.gao@rock-chips.com |
|---|---|
| State | Superseded |
| Delegated to: | Simon Glass |
| Headers | show |
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> > On 02 May 2017, at 10:19, Eric Gao <eric.gao@rock-chips.com> wrote: > > Add GRF register declaration for mipi dsi. > > Signed-off-by: Eric Gao <eric.gao@rock-chips.com> > Reviewed-by: Simon Glass <sjg@chromium.org> > > --- > > Changes in v7: None > Changes in v6: None > Changes in v5: > -Modify indentation for better readability. > -Make all enum variate have explicit value. > > Changes in v4: None > Changes in v3: > -Split GRF changes as a single patch > > Changes in v2: None > > arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 29 ++++++++++++++++++++++--- > 1 file changed, 26 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h > index cbcff2e..387c1ff5 100644 > --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h > +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h > @@ -456,9 +456,32 @@ enum { > GRF_PWM_1 = 1, > > /* GRF_SOC_CON7 */ > - GRF_UART_DBG_SEL_SHIFT = 10, > - GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, > - GRF_UART_DBG_SEL_C = 2, > + GRF_UART_DBG_SEL_SHIFT = 10, > + GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, > + GRF_UART_DBG_SEL_C = 2, > + > + /* GRF_SOC_CON20 */ > + GRF_DSI0_VOP_SEL_SHIFT = 0, > + GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, > + GRF_DSI0_VOP_SEL_B = 0, > + GRF_DSI0_VOP_SEL_L = 1, > + > + /* GRF_SOC_CON22 */ > + GRF_DPHY_TX0_RXMODE_SHIFT = 0, > + GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, > + GRF_DPHY_TX0_RXMODE_EN = 0xb, > + GRF_DPHY_TX0_RXMODE_DIS = 0, > + > + GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, > + GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, > + GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, > + GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, > + > + GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, > + GRF_DPHY_TX0_TURNREQUEST_MASK = > + 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT, > + GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, > + GRF_DPHY_TX0_TURNREQUEST_DIS = 0, > > /* PMUGRF_GPIO0A_IOMUX */ > PMUGRF_GPIO0A6_SEL_SHIFT = 12, > -- > 1.9.1 > >
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index cbcff2e..387c1ff5 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -456,9 +456,32 @@ enum { GRF_PWM_1 = 1, /* GRF_SOC_CON7 */ - GRF_UART_DBG_SEL_SHIFT = 10, - GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, - GRF_UART_DBG_SEL_C = 2, + GRF_UART_DBG_SEL_SHIFT = 10, + GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, + GRF_UART_DBG_SEL_C = 2, + + /* GRF_SOC_CON20 */ + GRF_DSI0_VOP_SEL_SHIFT = 0, + GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, + GRF_DSI0_VOP_SEL_B = 0, + GRF_DSI0_VOP_SEL_L = 1, + + /* GRF_SOC_CON22 */ + GRF_DPHY_TX0_RXMODE_SHIFT = 0, + GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, + GRF_DPHY_TX0_RXMODE_EN = 0xb, + GRF_DPHY_TX0_RXMODE_DIS = 0, + + GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, + GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, + GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, + GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, + + GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, + GRF_DPHY_TX0_TURNREQUEST_MASK = + 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT, + GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, + GRF_DPHY_TX0_TURNREQUEST_DIS = 0, /* PMUGRF_GPIO0A_IOMUX */ PMUGRF_GPIO0A6_SEL_SHIFT = 12,