diff --git a/MAINTAINERS b/MAINTAINERS
index 0590ad9..c87ca56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1085,6 +1085,9 @@ Peter Meerwald <devel@bct-electronic.com>
 
 	bct-brettl2	BF536
 
+Jason Liu <r64343@freescale.com>
+
+	MX53evk         i.MX53
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index 5725c30..7b6ab66 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -34,6 +34,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text	:
 	{
+		*(.ivt)
 		arch/arm/cpu/armv7/start.o	(.text)
 		*(.text)
 	}
diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile
new file mode 100755
index 0000000..c6dc1cd
--- /dev/null
+++ b/board/freescale/mx53evk/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx53evk.o
+SOBJS	:= ivt.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53evk/config.mk b/board/freescale/mx53evk/config.mk
new file mode 100755
index 0000000..2b21a08
--- /dev/null
+++ b/board/freescale/mx53evk/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x77800000
diff --git a/board/freescale/mx53evk/ivt.S b/board/freescale/mx53evk/ivt.S
new file mode 100755
index 0000000..f7a176f
--- /dev/null
+++ b/board/freescale/mx53evk/ivt.S
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * .word with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.section ".ivt"
+
+ivt_header:         .word 0x402000D1    /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:    .word (0xF8006400 + (plugin_start - CONFIG_SYS_TEXT_BASE))
+reserv1:            .word 0x0
+dcd_ptr:            .word 0x0
+boot_data_ptr:      .word (0xF8006400 + (boot_data - CONFIG_SYS_TEXT_BASE))
+self_ptr:           .word (0xF8006400 + (ivt_header - CONFIG_SYS_TEXT_BASE))
+app_code_csf:       .word 0x0
+reserv2:            .word 0x0
+boot_data:          .word 0xF8006000
+image_len:          .word 2*1024
+plugin:             .word 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:        .word 0x402000D1    /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:   .word _start        /*Entry point for the bootloader */
+reserv3:            .word 0x0
+dcd2_ptr:           .word 0x0
+boot_data2_ptr:     .word boot_data2
+self_ptr2:          .word ivt2_header
+app_code_csf2:      .word 0x0
+reserv4:            .word 0x0
+boot_data2:         .word (CONFIG_SYS_TEXT_BASE - 0x400)
+image_len2:         .word (_end - CONFIG_SYS_TEXT_BASE)
+plugin2:            .word 0x0
+
+
+/* Here starts the plugin code */
+plugin_start:
+	/* Save the return address and the function arguments */
+	push {r0-r3, lr}
+
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+
+	cmp r1, #0x20
+
+	/* IOMUX Setup */
+	ldr r0, =0x53fa8500
+	moveq r1, #0x00180000
+	movne r1, #0x00380000
+	mov r2, #0x00380000
+	add r2, r2, #0x40
+	add r3, r1, #0x40
+	mov r4, #0x00200000
+
+	str r1, [r0, #0x54]
+	str r2, [r0, #0x58]
+	str r1, [r0, #0x60]
+	str r3, [r0, #0x64]
+	str r2, [r0, #0x68]
+
+	streq r1, [r0, #0x70]
+	strne r4, [r0, #0x70]
+	str r1, [r0, #0x74]
+	streq r1, [r0, #0x78]
+	strne r4, [r0, #0x78]
+	str r2, [r0, #0x7c]
+	str r3, [r0, #0x80]
+	str r1, [r0, #0x84]
+	str r1, [r0, #0x88]
+	str r2, [r0, #0x90]
+	str r1, [r0, #0x94]
+
+	ldr r0, =0x53fa86f0
+	str r1, [r0, #0x0]
+	mov r2, #0x00000200
+	str r2, [r0, #0x4]
+	mov r2, #0x00000000
+	str r2, [r0, #0xc]
+
+	ldr r0, =0x53fa8700
+	str r2, [r0, #0x14]
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+	str r1, [r0, #0x20]
+
+	moveq r2, #0x02000000
+	movne r2, #0x06000000
+
+	str r2, [r0, #0x24]
+	str r1, [r0, #0x28]
+	str r1, [r0, #0x2c]
+
+	/* Initialize DDR2 memory - Hynix H5PS2G83AFR */
+	ldr r0, =ESDCTL_BASE_ADDR
+
+	ldreq r1, =0x31333530
+	ldrne r1, =0x2b2f3031
+	str r1, [r0, #0x088]
+
+	ldreq r1, =0x4a474a44
+	ldrne r1, =0x40363333
+	str r1, [r0, #0x090]
+
+	/* add 3 logic unit of delay to sdclk  */
+	ldr r1, =0x00000f00
+	str r1, [r0, #0x098]
+
+	ldr r1, =0x00000800
+	str r1, [r0, #0x0F8]
+
+	ldreq r1, =0x02490241
+	ldrne r1, =0x01310132
+	str r1, [r0, #0x07c]
+
+	ldreq r1, =0x01710171
+	ldrne r1, =0x0133014b
+	str r1, [r0, #0x080]
+
+	/* Enable bank interleaving, RALAT = 0x4, DDR2_EN = 1 */
+	ldr r1, =0x00001710
+	str r1, [r0, #0x018]
+
+	ldr r1, =0xc4110000
+	str r1, [r0, #0x00]
+
+	ldr r1, =0x4d5122d2
+	str r1, [r0, #0x0C]
+
+	ldr r1, =0x92d18a22
+	str r1, [r0, #0x10]
+
+	ldr r1, =0x00c70092
+	str r1, [r0, #0x14]
+
+	ldr r1, =0x000026d2
+	str r1, [r0, #0x2C]
+
+	ldr r1, =0x009f000e
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x12272000
+	str r1, [r0, #0x08]
+
+	ldr r1, =0x00030012
+	str r1, [r0, #0x04]
+
+	ldr r1, =0x04008010
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008032
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008033
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008031
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0b5280b0
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x04008010
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008020
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008020
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0a528030
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x03c68031
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00468031
+	str r1, [r0, #0x1C]
+
+	/* Even though Rev B does not have DDR on CSD1, keep these
+	 * mode register initialization sequences for future uses since
+	 * it does not hurt to keep them
+	 */
+	ldr r1, =0x04008018
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0000803a
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0000803b
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008039
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0b528138
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x04008018
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008028
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008028
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0a528038
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x03c68039
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00468039
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00005800
+	str r1, [r0, #0x20]
+
+	ldr r1, =0x00033337
+	str r1, [r0, #0x58]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1C]
+
+	/*
+	 * The following is to fill in those arguments for this ROM function pu_
+	 * irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+	 *
+	 * This function is used to copy data from the storage media into DDR.
+	 *
+	 * start - Initial (possibly partial) image load address on entry. Final
+	 *             image load address on exit.
+	 * bytes - Initial (possibly partial) image size on entry. Final image
+	 *             size on exit.
+	 * boot_data - Initial @ref ivt Boot Data load address.
+	 */
+	adr r0, DDR_DEST_ADDR
+	adr r1, COPY_SIZE
+	adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* Different ROM address for TO 1.0 & TO 2.0 */
+	moveq r4, #0x1800
+	addeq r4, r4, #0x4d
+	beq 2f
+	mov r4, #0x400000
+	add r4, r4, #0x5000
+	add r4, r4, #0xc7
+
+2:      blx r4 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* To return to ROM from plugin, we need to fill in these argument.
+	 * Here is what need to do:
+	 * Need to construct the param for the function before return to ROM:
+	 * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+	 */
+	pop {r0-r3, lr}
+	ldr r4, DDR_DEST_ADDR
+	str r4, [r0]
+	ldr r4, COPY_SIZE
+	str r4, [r1]
+	mov r4, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r4, r4, #0x2C
+	str r4, [r2]
+	mov r0, #1
+
+	bx lr          /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   (CONFIG_SYS_TEXT_BASE - 0x400)
+COPY_SIZE:        .word   _end - CONFIG_SYS_TEXT_BASE
+BOOT_DATA:        .word   (CONFIG_SYS_TEXT_BASE - 0x400)
+                  .word   _end - CONFIG_SYS_TEXT_BASE
+                  .word   0
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
new file mode 100755
index 0000000..ff6bfb2
--- /dev/null
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+	switch (module_base) {
+	case I2C1_BASE_ADDR:
+		/* i2c1 SDA */
+		mxc_request_iomux(MX53_PIN_CSI0_D8,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		/* i2c1 SCL */
+		mxc_request_iomux(MX53_PIN_CSI0_D9,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		break;
+	case I2C2_BASE_ADDR:
+		/* i2c2 SDA */
+		mxc_request_iomux(MX53_PIN_KEY_ROW3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+		/* i2c2 SCL */
+		mxc_request_iomux(MX53_PIN_KEY_COL3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+		break;
+	default:
+		printf("Invalid I2C base: 0x%x\n", module_base);
+		break;
+	}
+}
+
+void power_init(void)
+{
+	unsigned char buf[4] = { 0 };
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/* Set core voltage VDDGP to 1.05V for 800MHZ */
+	buf[0] = 0x45;
+	buf[1] = 0x4a;
+	buf[2] = 0x52;
+	if (i2c_write(0x8, 24, 1, buf, 3))
+		return;
+
+	/* Set DDR voltage VDDA to 1.25V */
+	buf[0] = 0;
+	buf[1] = 0;
+	buf[2] = 0x1a;
+	if (i2c_write(0x8, 26, 1, buf, 3))
+		return;
+
+	if (is_soc_rev(CHIP_REV_2_0) == 0) {
+		/* Set VCC to 1.3V for TO2 */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1C;
+		if (i2c_write(0x8, 25, 1, buf, 3))
+			return;
+
+		/* Set VDDA to 1.3V for TO2 */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1C;
+		if (i2c_write(0x8, 26, 1, buf, 3))
+			return;
+	}
+
+	/* need to delay 100 ms to allow power supplies to ramp-up */
+	udelay(100000);
+
+	/* Raise the core frequency to 800MHz */
+	writel(0x0, &mxc_ccm->cacrr);
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	 /* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+	{MMC_SDHC3_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = readl(GPIO3_BASE_ADDR) & 0x2000;
+	else
+		*cd = readl(GPIO3_BASE_ADDR) & 0x800;
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA3,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_EIM_DA13,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			break;
+		case 1:
+			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_IORDY,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA8,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA9,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA10,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA11,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA0,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA1,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA2,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA3,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_EIM_DA11,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_init(void)
+{
+	system_rev = get_cpu_rev();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_I2C_MXC
+	setup_i2c(CONFIG_SYS_I2C_PORT);
+	power_init();
+#endif
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: MX53EVK [");
+
+	switch (__REG(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		printf("POR");
+		break;
+	case 0x0009:
+		printf("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		printf("WDOG");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf("]\n");
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index dcd5a12..736e88e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -101,6 +101,7 @@ omap5912osk                  arm         arm926ejs   -                   ti
 edminiv2                     arm         arm926ejs   -                   LaCie          orion5x
 ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
 mx51evk                      arm         armv7       mx51evk             freescale      mx5
+mx53evk                      arm         armv7       mx53evk             freescale      mx5
 vision2                      arm         armv7       vision2             ttcontrol      mx5
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
new file mode 100755
index 0000000..d8b39ad
--- /dev/null
+++ b/include/configs/mx53evk.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+
+#define CONFIG_MX53
+
+#define CONFIG_SYS_MX5_HCLK	24000000
+#define CONFIG_SYS_MX5_CLK32		32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+
+#include <asm/arch/imx-regs.h>
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define BOARD_LATE_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX53_UART1
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C          1
+#define CONFIG_HARD_I2C         1
+#define CONFIG_I2C_MXC          1
+#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C_SLAVE            0xfe
+/*
+ * MMC Configs
+ * */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_PRIME	"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"MX53EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H */
