From patchwork Mon May 1 12:06:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Wunner X-Patchwork-Id: 757145 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wGjpW0wMNz9sNC for ; Mon, 1 May 2017 22:07:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423443AbdEAMHO (ORCPT ); Mon, 1 May 2017 08:07:14 -0400 Received: from mailout2.hostsharing.net ([83.223.90.233]:37665 "EHLO mailout2.hostsharing.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423442AbdEAMHN (ORCPT ); Mon, 1 May 2017 08:07:13 -0400 Received: from h08.hostsharing.net (h08.hostsharing.net [83.223.95.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mailout2.hostsharing.net (Postfix) with ESMTPS id 857CD10189B91; Mon, 1 May 2017 14:06:47 +0200 (CEST) Received: from localhost (5-38-90-81.adsl.cmo.de [81.90.38.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by h08.hostsharing.net (Postfix) with ESMTPSA id 80CB2603E052; Mon, 1 May 2017 14:07:09 +0200 (CEST) X-Mailbox-Line: From 2cf485a95fe875f1d6874a90e922e89dce173d77 Mon Sep 17 00:00:00 2001 Message-Id: <2cf485a95fe875f1d6874a90e922e89dce173d77.1493631639.git.lukas@wunner.de> In-Reply-To: References: From: Lukas Wunner Date: Mon, 1 May 2017 14:06:39 +0200 Subject: [PATCH 1/5] PCI: pciehp: Resume to D0 on board addition/removal To: Bjorn Helgaas , linux-pci@vger.kernel.org, Ashok Raj , Yinghai Lu Cc: "Rafael J. Wysocki" , Mika Westerberg , Erik Veijola , Keith Busch , Krishna Dhulipala , Wei Zhang Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hotplug ports need to be in D0 to access devices on their secondary bus. pciehp itself does this in pciehp_check_link_status(), pciehp_configure_device() (both called from board_added()) and pciehp_unconfigure_device() (called from remove_board()). In addition, Yinghai Lu discovered that some Skylake server CPUs or PCHs feature a Power Controller for their PCIe hotplug ports (PCIe r3.1, sec 6.7.1.8) which requires the port to be in D0 when invoking pciehp_power_on_slot() (likewise called from board_added()). The spec is silent about such a requirement, but it seems prudent to assume that any hotplug port with a Power Controller may need this. Thus, acquire a runtime PM ref for the invocation of board_added() and remove_board(). Cc: Rafael J. Wysocki Cc: Mika Westerberg Cc: Erik Veijola Cc: Ashok Raj Cc: Keith Busch Cc: Yinghai Lu Cc: Krishna Dhulipala Cc: Wei Zhang Signed-off-by: Lukas Wunner --- drivers/pci/hotplug/pciehp_ctrl.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c index ec0b4c11ccd9..d071aa63dac9 100644 --- a/drivers/pci/hotplug/pciehp_ctrl.c +++ b/drivers/pci/hotplug/pciehp_ctrl.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include "../pci.h" #include "pciehp.h" @@ -390,6 +391,7 @@ int pciehp_enable_slot(struct slot *p_slot) { u8 getstatus = 0; struct controller *ctrl = p_slot->ctrl; + int retval; pciehp_get_adapter_status(p_slot, &getstatus); if (!getstatus) { @@ -414,7 +416,10 @@ int pciehp_enable_slot(struct slot *p_slot) } } - return board_added(p_slot); + pm_runtime_get_sync(&ctrl->pcie->port->dev); + retval = board_added(p_slot); + pm_runtime_put(&ctrl->pcie->port->dev); + return retval; } /* @@ -424,6 +429,7 @@ int pciehp_disable_slot(struct slot *p_slot) { u8 getstatus = 0; struct controller *ctrl = p_slot->ctrl; + int retval; if (!p_slot->ctrl) return 1; @@ -437,7 +443,10 @@ int pciehp_disable_slot(struct slot *p_slot) } } - return remove_board(p_slot); + pm_runtime_get_sync(&ctrl->pcie->port->dev); + retval = remove_board(p_slot); + pm_runtime_put(&ctrl->pcie->port->dev); + return retval; } int pciehp_sysfs_enable_slot(struct slot *p_slot)