| Message ID | 20170501075139.19006-1-joel@jms.id.au |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Mon, 2017-05-01 at 17:21 +0930, Joel Stanley wrote: > This is required so the UART can be used before booting the host. > > > Signed-off-by: Joel Stanley <joel@jms.id.au> > > --- > This is a minimal workaround for manufacturing. dev-4.10 will receive a > proper fix. > > v2: > - Make it compile > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > > arch/arm/mach-aspeed/aspeed.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c > index 0717181cc890..0d1dded5d91b 100644 > --- a/arch/arm/mach-aspeed/aspeed.c > +++ b/arch/arm/mach-aspeed/aspeed.c > @@ -197,6 +197,8 @@ static void __init do_zaius_setup(void) > > static void __init do_witherspoon_setup(void) > { > > + int reg; > + > > do_common_setup(); > > > /* Setup PNOR address mapping for 64M flash > @@ -216,6 +218,14 @@ static void __init do_witherspoon_setup(void) > > > /* Set SPI1 CE0 decoding window to 0x30000000 */ > > writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); > + > + /* Disable default behavior of UART1 being held in reset by LPCRST#. > + * By releasing UART1 from being controlled by LPC reset, it becomes > + * immediately available regardless of the host being up. > + */ > + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); > + /* Clear "Enable UART1 reset source from LPC" */ > + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); > } > > static void __init do_romulus_setup(void)
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c index 0717181cc890..0d1dded5d91b 100644 --- a/arch/arm/mach-aspeed/aspeed.c +++ b/arch/arm/mach-aspeed/aspeed.c @@ -197,6 +197,8 @@ static void __init do_zaius_setup(void) static void __init do_witherspoon_setup(void) { + int reg; + do_common_setup(); /* Setup PNOR address mapping for 64M flash @@ -216,6 +218,14 @@ static void __init do_witherspoon_setup(void) /* Set SPI1 CE0 decoding window to 0x30000000 */ writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); + + /* Disable default behavior of UART1 being held in reset by LPCRST#. + * By releasing UART1 from being controlled by LPC reset, it becomes + * immediately available regardless of the host being up. + */ + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); + /* Clear "Enable UART1 reset source from LPC" */ + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); } static void __init do_romulus_setup(void)