diff mbox

[U-Boot,1/2,v7] board: freescale: ls2080ardb: Update QIXIS code

Message ID 1493356295-9646-1-git-send-email-priyanka.jain@nxp.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Priyanka Jain April 28, 2017, 5:11 a.m. UTC 
Update QIXIS related code to be executed
only if CONFIG_FSL_QIXIS flag is enabled

As per board documentation, default sysclk is 100MHz.
In case QIXIS code is not enabled,
update default sysclk value to 100MHz

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 Changes for v4:
 	Added changes for default sysclk as 100MHz

 board/freescale/ls2080ardb/ls2080ardb.c |   21 +++++++++++++++++----
 1 files changed, 17 insertions(+), 4 deletions(-)

Comments

York Sun May 25, 2017, 3:02 p.m. UTC | #1 
On 04/27/2017 10:11 PM, Priyanka Jain wrote:
> Update QIXIS related code to be executed
> only if CONFIG_FSL_QIXIS flag is enabled
>
> As per board documentation, default sysclk is 100MHz.
> In case QIXIS code is not enabled,
> update default sysclk value to 100MHz
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> ---
>  Changes for v4:
>  	Added changes for default sysclk as 100MHz
>
>  board/freescale/ls2080ardb/ls2080ardb.c |   21 +++++++++++++++++----
>  1 files changed, 17 insertions(+), 4 deletions(-)

Reformatted commit message. Applied to fsl-qoriq master, awaiting upstream.

York
diff mbox

Patch

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 52adca0..1379b81 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -23,8 +23,10 @@ 
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 
+#ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
+#endif
 #include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
@@ -58,12 +60,15 @@  unsigned long long get_qixis_addr(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
+#endif
 	char buf[15];
 
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
@@ -79,7 +84,7 @@  int checkboard(void)
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
+#endif
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
@@ -93,6 +98,7 @@  int checkboard(void)
 
 unsigned long get_board_sys_clk(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch (sysclk_conf & 0x0F) {
@@ -111,7 +117,8 @@  unsigned long get_board_sys_clk(void)
 	case QIXIS_SYSCLK_166:
 		return 166666666;
 	}
-	return 66666666;
+#endif
+	return 100000000;
 }
 
 int select_i2c_ch_pca9547(u8 ch)
@@ -134,6 +141,7 @@  int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int config_board_mux(int ctrl_type)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 reg5;
 
 	reg5 = QIXIS_READ(brdcfg[5]);
@@ -151,7 +159,7 @@  int config_board_mux(int ctrl_type)
 	}
 
 	QIXIS_WRITE(brdcfg[5], reg5);
-
+#endif
 	return 0;
 }
 
@@ -181,8 +189,9 @@  int board_init(void)
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#ifdef CONFIG_FSL_QIXIS
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
+#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
@@ -319,6 +328,7 @@  int ft_board_setup(void *blob, bd_t *bd)
 
 void qixis_dump_switch(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	int i, nr_of_cfgsw;
 
 	QIXIS_WRITE(cms[0], 0x00);
@@ -329,6 +339,7 @@  void qixis_dump_switch(void)
 		QIXIS_WRITE(cms[0], i);
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
+#endif
 }
 
 /*
@@ -339,6 +350,7 @@  void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -348,4 +360,5 @@  void update_spd_address(unsigned int ctrl_num,
 		else if (ctrl_num == 1 && slot == 1)
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
+#endif
 }