| Message ID | 20170426051358.1909-1-chen.kenyy@inventec.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
Hi Ken, Thank you for your patch. I have some questions below. On Wed, Apr 26, 2017 at 2:43 PM, Ken Chen <chen.kenyy@inventec.com> wrote: > Modify Lanyang dts and add lanyang initial in aspeed.c > > Signed-off-by: Ken Chen <chen.kenyy@inventec.com> > --- > arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts | 13 +++--- > arch/arm/mach-aspeed/aspeed.c | 65 ++++++++++++++++++++++++++++ > 2 files changed, 71 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts > index 176e4b4..6456458 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts > @@ -1,4 +1,4 @@ > -/dts-v1/; > +/dts-v3/; > > #include "aspeed-g5.dtsi" > #include <dt-bindings/gpio/aspeed-gpio.h> > @@ -302,18 +302,17 @@ > }; > > &gpio { > - line_apss_reset { > - gpio-hog; > - gpios = <ASPEED_GPIO(E, 4) GPIO_ACTIVE_HIGH>; > - output-high; > - line-name = "BMC_APSS_RESET_N"; > - }; > + > }; > > &vuart { > status = "okay"; > }; > > +&gfx { > + status = "okay"; > +}; > + > &pinctrl { > aspeed,external-nodes = <&gfx &lhc>; > }; > diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c > index a7b03a0..b1073e5 100644 > --- a/arch/arm/mach-aspeed/aspeed.c > +++ b/arch/arm/mach-aspeed/aspeed.c > @@ -238,6 +238,69 @@ static void __init do_romulus_setup(void) > writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); > } > > +static void __init do_lanyang_setup(void) > +{ > + unsigned long reg; > + unsigned long board_rev; > + /* D3 in GPIOA/B/C/D direction and data registers */ > + unsigned long phy_reset_mask = BIT(27); > + > + do_common_setup(); > + > + /* Read BOARD_REV[4:0] fuses from GPIOM[7:3] */ > + reg = readl(AST_IO(AST_BASE_GPIO | 0x78)); > + board_rev = (reg >> 3) & 0x1F; Can you check that the board uses GPIOM for revision GPIOs? The version of the schematic that I saw does not. > + > + /* EVT1 hacks */ > + if (board_rev == 0) { > + /* Disable GPIO I, G/AB pulldowns due to weak driving buffers */ > + reg = readl(AST_IO(AST_BASE_SCU | 0x8C)); > + writel(reg | BIT(24) | BIT(22), AST_IO(AST_BASE_SCU | 0x8C)); > + } > + > + /* Disable GPIO H/AC pulldowns to float 1-wire interface pins */ > + reg = readl(AST_IO(AST_BASE_SCU | 0x8C)); > + writel(reg | BIT(23), AST_IO(AST_BASE_SCU | 0x8C)); > + > + /* Assert MAC2 PHY hardware reset */ It looks like GPIOD3 is not used for PHY hardware reset. > + /* Set pin low */ > + reg = readl(AST_IO(AST_BASE_GPIO | 0x00)); > + writel(reg & ~phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00)); > + /* Enable pin for output */ > + reg = readl(AST_IO(AST_BASE_GPIO | 0x04)); > + writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x04)); > + udelay(3); > + /* Set pin high */ > + reg = readl(AST_IO(AST_BASE_GPIO | 0x00)); > + writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00)); > + > + /* Setup PNOR address mapping for 64M flash > + * > + * ADRBASE: 0x3000 (0x30000000) > + * HWMBASE: 0x0C00 (0x0C000000) > + * ADDRMASK: 0xFC00 (0xFC000000) > + * HWNCARE: 0x03FF (0x03FF0000) > + * > + * Mapping appears at 0x60300fc000000 on the host > + */ > + writel(0x30000C00, AST_IO(AST_BASE_LPC | 0x88)); > + writel(0xFC0003FF, AST_IO(AST_BASE_LPC | 0x8C)); > + > + /* Set SPI1 CE1 decoding window to 0x34000000 */ > + writel(0x70680000, AST_IO(AST_BASE_SPI | 0x34)); > + > + /* Set SPI1 CE0 decoding window to 0x30000000 */ > + writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); We should not need to do this. mboxd will set them. Cheers, Joel > + > + /* Disable default behavior of UART1 being held in reset by LPCRST#. > + * By releasing UART1 from being controlled by LPC reset, it becomes > + * immediately available regardless of the host being up. > + */ > + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); > + /* Clear "Enable UART1 reset source from LPC" */ > + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); > +} > + > #define SCU_PASSWORD 0x1688A8A8 > > static void __init aspeed_init_early(void) > @@ -275,6 +338,8 @@ static void __init aspeed_init_early(void) > do_witherspoon_setup(); > if (of_machine_is_compatible("ibm,romulus-bmc")) > do_romulus_setup(); > + if (of_machine_is_compatible("inventec,lanyang-bmc")) > + do_romulus_setup(); > } > > static void __init aspeed_map_io(void) > -- > 2.9.3 >
On Wed, 2017-04-26 at 17:45 +0930, Joel Stanley wrote: > Hi Ken, > > Thank you for your patch. I have some questions below. > > > On Wed, Apr 26, 2017 at 2:43 PM, Ken Chen <chen.kenyy@inventec.com> wrote: > > > > + /* Setup PNOR address mapping for 64M flash > > + * > > + * ADRBASE: 0x3000 (0x30000000) > > + * HWMBASE: 0x0C00 (0x0C000000) > > + * ADDRMASK: 0xFC00 (0xFC000000) > > + * HWNCARE: 0x03FF (0x03FF0000) > > + * > > + * Mapping appears at 0x60300fc000000 on the host > > + */ > > + writel(0x30000C00, AST_IO(AST_BASE_LPC | 0x88)); > > + writel(0xFC0003FF, AST_IO(AST_BASE_LPC | 0x8C)); > > + > > + /* Set SPI1 CE1 decoding window to 0x34000000 */ > > + writel(0x70680000, AST_IO(AST_BASE_SPI | 0x34)); > > + > > + /* Set SPI1 CE0 decoding window to 0x30000000 */ > > + writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); > > We should not need to do this. mboxd will set them. To clarify, there are two different cases here, but the outcome remains that we don't need the above. We don't need to set the two LPC registers because mboxd will set them via the interface exposed by drivers/misc/aspeed-lpc-ctrl.c. We also don't need to set the two SPI registers because the SMC driver will configure them based on the chip(s) detected on the bus during driver probe. Cheers, Andrew
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index 176e4b4..6456458 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -1,4 +1,4 @@ -/dts-v1/; +/dts-v3/; #include "aspeed-g5.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> @@ -302,18 +302,17 @@ }; &gpio { - line_apss_reset { - gpio-hog; - gpios = <ASPEED_GPIO(E, 4) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "BMC_APSS_RESET_N"; - }; + }; &vuart { status = "okay"; }; +&gfx { + status = "okay"; +}; + &pinctrl { aspeed,external-nodes = <&gfx &lhc>; }; diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c index a7b03a0..b1073e5 100644 --- a/arch/arm/mach-aspeed/aspeed.c +++ b/arch/arm/mach-aspeed/aspeed.c @@ -238,6 +238,69 @@ static void __init do_romulus_setup(void) writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); } +static void __init do_lanyang_setup(void) +{ + unsigned long reg; + unsigned long board_rev; + /* D3 in GPIOA/B/C/D direction and data registers */ + unsigned long phy_reset_mask = BIT(27); + + do_common_setup(); + + /* Read BOARD_REV[4:0] fuses from GPIOM[7:3] */ + reg = readl(AST_IO(AST_BASE_GPIO | 0x78)); + board_rev = (reg >> 3) & 0x1F; + + /* EVT1 hacks */ + if (board_rev == 0) { + /* Disable GPIO I, G/AB pulldowns due to weak driving buffers */ + reg = readl(AST_IO(AST_BASE_SCU | 0x8C)); + writel(reg | BIT(24) | BIT(22), AST_IO(AST_BASE_SCU | 0x8C)); + } + + /* Disable GPIO H/AC pulldowns to float 1-wire interface pins */ + reg = readl(AST_IO(AST_BASE_SCU | 0x8C)); + writel(reg | BIT(23), AST_IO(AST_BASE_SCU | 0x8C)); + + /* Assert MAC2 PHY hardware reset */ + /* Set pin low */ + reg = readl(AST_IO(AST_BASE_GPIO | 0x00)); + writel(reg & ~phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00)); + /* Enable pin for output */ + reg = readl(AST_IO(AST_BASE_GPIO | 0x04)); + writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x04)); + udelay(3); + /* Set pin high */ + reg = readl(AST_IO(AST_BASE_GPIO | 0x00)); + writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00)); + + /* Setup PNOR address mapping for 64M flash + * + * ADRBASE: 0x3000 (0x30000000) + * HWMBASE: 0x0C00 (0x0C000000) + * ADDRMASK: 0xFC00 (0xFC000000) + * HWNCARE: 0x03FF (0x03FF0000) + * + * Mapping appears at 0x60300fc000000 on the host + */ + writel(0x30000C00, AST_IO(AST_BASE_LPC | 0x88)); + writel(0xFC0003FF, AST_IO(AST_BASE_LPC | 0x8C)); + + /* Set SPI1 CE1 decoding window to 0x34000000 */ + writel(0x70680000, AST_IO(AST_BASE_SPI | 0x34)); + + /* Set SPI1 CE0 decoding window to 0x30000000 */ + writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); + + /* Disable default behavior of UART1 being held in reset by LPCRST#. + * By releasing UART1 from being controlled by LPC reset, it becomes + * immediately available regardless of the host being up. + */ + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); + /* Clear "Enable UART1 reset source from LPC" */ + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); +} + #define SCU_PASSWORD 0x1688A8A8 static void __init aspeed_init_early(void) @@ -275,6 +338,8 @@ static void __init aspeed_init_early(void) do_witherspoon_setup(); if (of_machine_is_compatible("ibm,romulus-bmc")) do_romulus_setup(); + if (of_machine_is_compatible("inventec,lanyang-bmc")) + do_romulus_setup(); } static void __init aspeed_map_io(void)
Modify Lanyang dts and add lanyang initial in aspeed.c Signed-off-by: Ken Chen <chen.kenyy@inventec.com> --- arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts | 13 +++--- arch/arm/mach-aspeed/aspeed.c | 65 ++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+), 7 deletions(-)