From patchwork Tue Dec 14 14:05:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Lin Tang X-Patchwork-Id: 75491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 7FA82B6F10 for ; Wed, 15 Dec 2010 01:05:33 +1100 (EST) Received: (qmail 27297 invoked by alias); 14 Dec 2010 14:05:26 -0000 Received: (qmail 27233 invoked by uid 22791); 14 Dec 2010 14:05:24 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 14 Dec 2010 14:05:19 +0000 Received: (qmail 23992 invoked from network); 14 Dec 2010 14:05:17 -0000 Received: from unknown (HELO ?192.168.1.16?) (cltang@127.0.0.2) by mail.codesourcery.com with ESMTPA; 14 Dec 2010 14:05:17 -0000 Message-ID: <4D0779A3.6070200@codesourcery.com> Date: Tue, 14 Dec 2010 22:05:23 +0800 From: Chung-Lin Tang User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: gcc-patches Subject: [PATCH, ARM] Fix PR46883, ICE at reload X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, this patch tries to fix PR46883, where reload ICEs at an unrecognized insn. The failing insn is produced during split1. The "register_operand" predicate allows (subreg (mem)) before reload, which allows the zero_extend_qisi2 register splitter to hook on and create (subreg:QI (mem:HI (post_inc ...))), which causes reload to ICE (in two different places, depending on -O1 or -O2). While reload may need further work later, this patch changes the predicates above to use the ARM backend's "s_register_operand", which matches only regs/subregs of regs. This resolves the ICE, and seems to more closely match the original intention of the splitters. The PR testcase triggers the ICE due to the QI/SI splitter, but I have fixed the HI/SI splitter too, as it seems to be analogous. Tested without regressions. Ok to commit? Thanks, Chung-Lin 2010-12-14 Chung-Lin Tang PR target/46883 * config/arm/arm.md (zero_extendhisi2 for register input splitter): Change "register_operand" to "s_register_operand". (zero_extendqisi2 for register input splitter): Same. Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 167797) +++ config/arm/arm.md (working copy) @@ -4137,8 +4137,8 @@ }) (define_split - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand" "") + (zero_extend:SI (match_operand:HI 1 "s_register_operand" "")))] "!TARGET_THUMB2 && !arm_arch6" [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] @@ -4244,8 +4244,8 @@ }) (define_split - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand" "") + (zero_extend:SI (match_operand:QI 1 "s_register_operand" "")))] "!arm_arch6" [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] Index: testsuite/gcc.target/arm/pr46883.c =================================================================== --- testsuite/gcc.target/arm/pr46883.c (revision 0) +++ testsuite/gcc.target/arm/pr46883.c (revision 0) @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -march=armv5te" } */ + +void bar (unsigned char *q, unsigned short *data16s, int len) +{ + int i; + + for (i = 0; i < len; i++) + { + q[2 * i] = + (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF)) & 0xFF; + q[2 * i + 1] = + ((unsigned short) + (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF))) >> 8; + } +}