Patchwork [U-Boot,V2,07/12] PM856: Rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE

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Submitter Becky Bruce
Date Dec. 13, 2010, 9:06 p.m.
Message ID <1292274412-11340-8-git-send-email-beckyb@kernel.crashing.org>
Download mbox | patch
Permalink /patch/75414/
State Not Applicable
Delegated to: Kumar Gala
Headers show

Comments

Becky Bruce - Dec. 13, 2010, 9:06 p.m.
This board does not actually configure anything for SDRAM - change
the name to avoid confusion and make it easier to go to a common
initdram going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 board/pm856/law.c       |    5 ++---
 board/pm856/tlb.c       |    4 ++--
 include/configs/PM856.h |    6 +-----
 3 files changed, 5 insertions(+), 10 deletions(-)
Kumar Gala - Dec. 14, 2010, 4:28 a.m.
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:

> This board does not actually configure anything for SDRAM - change
> the name to avoid confusion and make it easier to go to a common
> initdram going forward.
> 
> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
> ---
> board/pm856/law.c       |    5 ++---
> board/pm856/tlb.c       |    4 ++--
> include/configs/PM856.h |    6 +-----
> 3 files changed, 5 insertions(+), 10 deletions(-)

drop as I'm killing support for this board.

- k

Patch

diff --git a/board/pm856/law.c b/board/pm856/law.c
index ac21d7a..bea9259 100644
--- a/board/pm856/law.c
+++ b/board/pm856/law.c
@@ -35,7 +35,7 @@ 
  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
  * 0xe000_0000     0xe000_ffff     CCSR                    1M
  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf000_0000     0xf7ff_ffff     LBC                     128M
  * 0xf800_0000     0xf80f_ffff     BCSR                    1M
  * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       64M
  *
@@ -49,8 +49,7 @@  struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c
index 5e74e2d..dadb75c 100644
--- a/board/pm856/tlb.c
+++ b/board/pm856/tlb.c
@@ -93,9 +93,9 @@  struct fsl_e_tlb_entry tlb_table[] = {
 
 	/*
 	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
+	 * 0xf000_0000	64M	LBC
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index d3e8f41..dbce6c4 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -125,11 +125,7 @@ 
 #define CONFIG_SYS_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
 #define CONFIG_SYS_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
 
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
+#define CONFIG_SYS_LBC_BASE	0xf0000000	/* Localbus */
 
 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
 #define CONFIG_SYS_BR0_PRELIM		0xfe001801	/* port size 32bit */