From patchwork Fri Apr 21 14:24:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 753444 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w8dTz0KlXz9s4s for ; Sat, 22 Apr 2017 00:31:50 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="T2wG3XAG"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id ACA48C21C92; Fri, 21 Apr 2017 14:23:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8AAB4C21D2C; Fri, 21 Apr 2017 14:21:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 92841C21CAC; Fri, 21 Apr 2017 14:21:15 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id DDF72C21CC3 for ; Fri, 21 Apr 2017 14:21:11 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id w50so7727830wrc.0 for ; Fri, 21 Apr 2017 07:21:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=VzUyM/wYD7gJASsw+t+aKWuf6RHvukSr755Ta0jquYA=; b=T2wG3XAGlxETXt/ZT9dG2e5Z4DnJiGhK7RRqQVGUq5biZcgNzaag+T7n6qsgjkng9c As5yu1/0dFsM3qMvN2fTLd3qyR6F+au0WHpK3nwtiOe4G7aMJgFWCp4i+n2FusjobjOt f3F0onkdVxOL1cmVscK0uGVVslRJAg1vf9miR9cq1oe71+2bKo/MrNcW3C3DEiCViHxY 1UjyEZ+5ZJ/pJHYGIU86RIsLfMQBdY0K9Xrl076eF8Ih1+bvOX7gs2T8YJwxboYsGUOi VyKy+p0MroOUu/o2sr3fxWAoNFZFrSYcu6A47tupZ1frZIHE0S9Us+fknZPzaeazzRG2 /6kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=VzUyM/wYD7gJASsw+t+aKWuf6RHvukSr755Ta0jquYA=; b=qAe51oIVO0A52UhVgwdzIvb9PH+TTZglZA9NpbjThJ1dyL3LzKVUZP9mlYN0druy7d EG5bfqf6s4Z9I1EJTTQI/6FPkZWZqG8nGgitoa1hv/9nELmgJDd5/jmPTJLNPanEE1AY 6kcO0zJfhZOwXbvZwSQxiU1ESeCxaMt8n7G/qjEXPYrLtmVhYQEEFU9dBLFTRb9Ar9U5 aiW6WXpiEOGfhsxihiImetZqZxFshb8A+Ae5jrYPTk1CptpzY2k2MmUU7q2RKmk9S7Ph IHyohbVJWEw3DYBJq21KRXMzqKfRwHq19hlm57vNub8QeGcVrfqAxwEAakGeeR2R1FvG V8wQ== X-Gm-Message-State: AN3rC/7wQiFDDUsfL3VuJX4NA/nlvIF8g1xsKWHmUFMyKiFBUw6lSAKD ++KGJQJWEzF6OQ== X-Received: by 10.223.155.210 with SMTP id e18mr12546458wrc.165.1492784471544; Fri, 21 Apr 2017 07:21:11 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id 4sm464843edt.64.2017.04.21.07.21.09 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 21 Apr 2017 07:21:10 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , U-Boot Mailing List Date: Fri, 21 Apr 2017 07:24:35 -0700 Message-Id: <1492784689-15701-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1492784689-15701-1-git-send-email-bmeng.cn@gmail.com> References: <1492784689-15701-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v2 08/22] x86: acpi: Add wake up assembly stub X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a wake up stub before jumping to OS wake up vector. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- Changes in v2: - add brackets around the second x in RELOCATED(x) macro - word-wrap to use more columns - change to use present tense in the comments arch/x86/cpu/Makefile | 1 + arch/x86/cpu/wakeup.S | 78 ++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/acpi_s3.h | 9 +++++ 3 files changed, 88 insertions(+) create mode 100644 arch/x86/cpu/wakeup.S diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 92a9023..e1c84ce 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -45,6 +45,7 @@ ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o endif obj-y += turbo.o +obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.o ifeq ($(CONFIG_$(SPL_)X86_64),y) obj-y += x86_64/ diff --git a/arch/x86/cpu/wakeup.S b/arch/x86/cpu/wakeup.S new file mode 100644 index 0000000..066c9b1 --- /dev/null +++ b/arch/x86/cpu/wakeup.S @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017, Bin Meng + * + * From coreboot src/arch/x86/wakeup.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define RELOCATED(x) ((x) - __wakeup + WAKEUP_BASE) + +#define CODE_SEG (X86_GDT_ENTRY_16BIT_CS * X86_GDT_ENTRY_SIZE) +#define DATA_SEG (X86_GDT_ENTRY_16BIT_DS * X86_GDT_ENTRY_SIZE) + + .code32 + .globl __wakeup +__wakeup: + /* First prepare the jmp to the resume vector */ + mov 0x4(%esp), %eax /* vector */ + /* last 4 bits of linear addr are taken as offset */ + andw $0x0f, %ax + movw %ax, (__wakeup_offset) + mov 0x4(%esp), %eax + /* the rest is taken as segment */ + shr $4, %eax + movw %ax, (__wakeup_segment) + + /* Activate the right segment descriptor real mode */ + ljmp $CODE_SEG, $RELOCATED(1f) +1: + /* 16 bit code from here on... */ + .code16 + + /* + * Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ + mov $DATA_SEG, %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Turn off protection */ + movl %cr0, %eax + andl $~X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now really going into real mode */ + ljmp $0, $RELOCATED(1f) +1: + movw $0x0, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* + * This is a FAR JMP to the OS waking vector. + * The C code changes the address to be correct. + */ + .byte 0xea + +__wakeup_offset = RELOCATED(.) + .word 0x0000 + +__wakeup_segment = RELOCATED(.) + .word 0x0000 + + .globl __wakeup_size +__wakeup_size: + .long . - __wakeup diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h index 10cedde..a06466c 100644 --- a/arch/x86/include/asm/acpi_s3.h +++ b/arch/x86/include/asm/acpi_s3.h @@ -7,6 +7,8 @@ #ifndef __ASM_ACPI_S3_H__ #define __ASM_ACPI_S3_H__ +#define WAKEUP_BASE 0x600 + /* PM1_STATUS register */ #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) @@ -27,6 +29,11 @@ #define SLP_TYP_S4 6 #define SLP_TYP_S5 7 +#ifndef __ASSEMBLY__ + +extern char __wakeup[]; +extern int __wakeup_size; + enum acpi_sleep_state { ACPI_S0, ACPI_S1, @@ -92,4 +99,6 @@ enum acpi_sleep_state chipset_prev_sleep_state(void); */ void chipset_clear_sleep_state(void); +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_ACPI_S3_H__ */