From patchwork Fri Apr 21 14:24:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 753427 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w8dJ45bvgz9s2x for ; Sat, 22 Apr 2017 00:23:16 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gKfhFdv6"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 54172C21CE8; Fri, 21 Apr 2017 14:21:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D742DC21CF4; Fri, 21 Apr 2017 14:21:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C29E7C21CC3; Fri, 21 Apr 2017 14:21:04 +0000 (UTC) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by lists.denx.de (Postfix) with ESMTPS id 42C05C21CBB for ; Fri, 21 Apr 2017 14:21:00 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id d79so5185379wmi.2 for ; Fri, 21 Apr 2017 07:21:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=rHUEPRaumPVWVS9QgL4Xu5QRB9pW2sfyldlBRtNGJv0=; b=gKfhFdv6BG6vSy59g6lgb9s5tqWM6Xc1JVNeS0k8n9uJDJkO0BQ9QgCaYXODgpYAFA lwNTL2nb355m8VD/nnHJZt6mko2m+89ThkWVIQQVa1/0aBYMRxSVFyGN4IPyd4o1RZ3k h8oxOEy8OSCbHomxf0H0SELkepgIBjwDNRPISRmLyuJb7uTKt+O6XMy8lHmKvrnDBwMO Xvdu8e3C3YntePxt7CFczfXBW+Z8E5QDD3HYYoFMLfchTLM68lIR6L7J3aWuHE1gMiDB KdnKVUPZdcEnpwGMUp2lT7PEnU13Zq3ugdkC8PA41nkzKNgiRlcXG1IxQIEfOq/QGqR7 Gfzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=rHUEPRaumPVWVS9QgL4Xu5QRB9pW2sfyldlBRtNGJv0=; b=HA50BbrTXZvOGyTC7WADrnGsQ6uDsgpeb352gZBJBeUjTy5h/dN+UfpsoMYnDazp78 KaxdMhz/ihPJriRgNJZvsSE0KUJ4jObqFwBUYEXGVfAUaFS7Rl1svgB4yyvb7RtYYOLB STkAFoJ59RJbpJ109eN8wf8Y7nd8I9IYhaOy+v1aOKn4hR0qD5I0wBN8TQOaFNjVPX0W t3HuaIEGe8zh74UIecU/w288f9x172JSxMaH7eHXsqACsXX4ejou3HVyTpmpRpxda5mE IiM2q5lKa8iMgrJaHh6SDFvcgnoX5VLomd3/+tDoVkD33cCvnpsRJLMASyk4jBLo9vH5 Xdtw== X-Gm-Message-State: AN3rC/4p/G8BfVkn3CFrjLXhfVoP8wCKGzfPkehZ3q0AiXkOTJcj9Gyy zIWwKFcTCCQA3A== X-Received: by 10.80.148.119 with SMTP id q52mr59335eda.174.1492784459924; Fri, 21 Apr 2017 07:20:59 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id 4sm464843edt.64.2017.04.21.07.20.57 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 21 Apr 2017 07:20:58 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , U-Boot Mailing List Date: Fri, 21 Apr 2017 07:24:29 -0700 Message-Id: <1492784689-15701-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1492784689-15701-1-git-send-email-bmeng.cn@gmail.com> References: <1492784689-15701-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v2 02/22] x86: baytrail: acpi: Add APIs for determining/clearing sleep state X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds APIs for determining previous sleep state from ACPI I/O registers, as well as clearing sleep state on BayTrail SoC. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- Changes in v2: None arch/x86/cpu/baytrail/acpi.c | 47 ++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-baytrail/iomap.h | 24 +++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index fa92d88..55ed7de 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -8,7 +8,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -187,3 +189,48 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) else gnvs->iuart_en = 0; } + +#ifdef CONFIG_HAVE_ACPI_RESUME +/* + * The following two routines are called at a very early stage, even before + * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS + * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses + * of these two blocks are programmed by either U-Boot or FSP. + * + * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S) + * on Intel BayTrail SoC already initializes these two base addresses so + * we are safe to access these registers here. + */ + +enum acpi_sleep_state chipset_prev_sleep_state(void) +{ + u32 pm1_sts; + u32 pm1_cnt; + u32 gen_pmcon1; + enum acpi_sleep_state prev_sleep_state = ACPI_S0; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1); + + debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) + prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt); + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void chipset_clear_sleep_state(void) +{ + u32 pm1_cnt; + + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); +} +#endif diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h index 62a9105..ec4e9d5 100644 --- a/arch/x86/include/asm/arch-baytrail/iomap.h +++ b/arch/x86/include/asm/arch-baytrail/iomap.h @@ -35,6 +35,27 @@ #define PMC_BASE_ADDRESS 0xfed03000 #define PMC_BASE_SIZE 0x400 +#define GEN_PMCON1 0x20 +#define UART_EN (1 << 24) +#define DISB (1 << 23) +#define MEM_SR (1 << 21) +#define SRS (1 << 20) +#define CTS (1 << 19) +#define MS4V (1 << 18) +#define PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define SUS_PWR_FLR (1 << 14) +#define WOL_EN_OVRD (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define GEN_RST_STS (1 << 9) +#define RPS (1 << 2) +#define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +#define SLPSX_STR_POL_LOCK (1 << 18) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) + /* Power Management Unit */ #define PUNIT_BASE_ADDRESS 0xfed05000 #define PUNIT_BASE_SIZE 0x800 @@ -62,6 +83,9 @@ #define ACPI_BASE_ADDRESS 0x0400 #define ACPI_BASE_SIZE 0x80 +#define PM1_STS 0x00 +#define PM1_CNT 0x04 + #define GPIO_BASE_ADDRESS 0x0500 #define GPIO_BASE_SIZE 0x100