[U-Boot,2/2,v3] nxp/ls2080ardb: Add QSPI-boot support

Message ID 1492773617-31302-1-git-send-email-priyanka.jain@nxp.com
State Superseded
Headers show

Commit Message

Priyanka Jain April 21, 2017, 11:20 a.m.
QSPI-boot is verified on LS20080ARDB RevF board
with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS
can not be access, so QIXIS flag is kept disabled

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
 Changes for v3:Udated README

 Changes for v2: Incorporated Sun York's comments
 Introduced another patch to update qixis related code
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |    1 +
 arch/arm/dts/Makefile                     |    2 +-
 arch/arm/dts/fsl-ls2080a-rdb-qspi.dts     |   57 +++++++++++++++++++++++++++++
 board/freescale/ls2080ardb/README         |   26 +++++++++++++
 configs/ls2080ardb_qspi_defconfig         |   40 ++++++++++++++++++++
 include/configs/ls2080a_common.h          |    6 +++
 include/configs/ls2080aqds.h              |    8 +----
 include/configs/ls2080ardb.h              |   56 ++++++++++++++++++++++++++++-
 8 files changed, 187 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls2080a-rdb-qspi.dts
 create mode 100644 configs/ls2080ardb_qspi_defconfig

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 12fd80e..4b32b2e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -163,6 +163,7 @@  endchoice
 config SYS_LS_PPA_FW_ADDR
 	hex "Address of PPA firmware loading from"
 	depends on FSL_LS_PPA
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
 	default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
 	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 	default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0ee4281..59366cf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,7 @@  dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
 	ls1021a-iot-duart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
-	fsl-ls2080a-rdb.dtb
+	fsl-ls2080a-rdb.dtb fsl-ls2080a-rdb-qspi.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts
new file mode 100644
index 0000000..aa9b03d
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts
@@ -0,0 +1,57 @@ 
+/*
+ * NXP ls2080a RDB board device tree source for QSPI-boot
+ *
+ * Copyright (C) 2017 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2080a RDB Board";
+	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fs512s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: s25fs512s@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	};
+};
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 0c9c574..c870adc 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -43,6 +43,7 @@  Memory map from core's view
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
 0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
 0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_2000_0000 .. 0x00_2FFF_FFFF	QSPI region #1
 0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
 0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
 0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
@@ -68,6 +69,31 @@  Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+c) QSPI boot
+
+cfg_rcw_src switches needs to be changed for booting from different option.
+Refer to board documentation for correct switch setting.
+
+QSPI boot details
+===================
+Supported only for
+ LS2080/LS2088ARDB RevF board with LS2088A SoC.
+
+Images needs to be copied to QSPI flash
+as per memory map given below.
+
+Memory map for QSPI flash
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01100000
 
 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
 -------------------------------------------------------------------
diff --git a/configs/ls2080ardb_qspi_defconfig b/configs/ls2080ardb_qspi_defconfig
new file mode 100644
index 0000000..d89c724
--- /dev/null
+++ b/configs/ls2080ardb_qspi_defconfig
@@ -0,0 +1,40 @@ 
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb-qspi"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 427f623..cdb416a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -28,6 +28,12 @@ 
 #else
 #define CONFIG_SYS_TEXT_BASE		0x30100000
 #endif
+#else
+#define CONFIG_SYS_TEXT_BASE		0x20100000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
 #endif
 
 #define CONFIG_SUPPORT_RAW_INITRD
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index beacb99..5e2c164 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -262,13 +262,7 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_TEXT_BASE		0x20010000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#else
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 2155a89..aa50f39 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -12,6 +12,12 @@ 
 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX       2
 
+#ifdef CONFIG_FSL_QSPI
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
+
 #define I2C_MUX_CH_VOL_MONITOR		0xa
 #define I2C_VOL_MONITOR_ADDR		0x38
 #define CONFIG_VOL_MONITOR_IR36021_READ
@@ -116,7 +122,9 @@  unsigned long get_board_sys_clk(void);
 					 CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
+#ifndef CONFIG_FSL_QSPI
 #define CONFIG_NAND_FSL_IFC
+#endif
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 
@@ -154,11 +162,15 @@  unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
+#ifndef CONFIG_FSL_QSPI
 #define CONFIG_CMD_NAND
+#endif
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
 
+#ifndef CONFIG_FSL_QSPI
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#endif
 #define QIXIS_LBMAP_SWITCH		0x06
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
@@ -241,11 +253,13 @@  unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
 #endif
+#endif
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
@@ -263,11 +277,18 @@  unsigned long get_board_sys_clk(void);
 #define I2C_MUX_CH_DEFAULT      0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+#endif
 
 /*
  * RTC configuration
@@ -347,6 +368,27 @@  unsigned long get_board_sys_clk(void);
 	" 0x580800000 \0"                       \
 	BOOTENV
 #else
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"scriptaddr=0x80800000\0"		\
+	"kernel_addr_r=0x81000000\0"		\
+	"pxefile_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x88000000\0"		\
+	"ramdisk_addr_r=0x89000000\0"		\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x21100000\0"		\
+	"mcmemsize=0x40000000\0"		\
+	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
+	"mcinitcmd=fsl_mc start mc 0x20a00000" \
+	" 0x20e00000 \0"                       \
+	BOOTENV
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"scriptaddr=0x80800000\0"		\
@@ -369,6 +411,7 @@  unsigned long get_board_sys_clk(void);
 	" 0x580800000 \0"                       \
 	BOOTENV
 #endif
+#endif
 
 
 #undef CONFIG_BOOTARGS
@@ -378,11 +421,18 @@  unsigned long get_board_sys_clk(void);
 				" hugepagesz=2m hugepages=256"
 
 #undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_QSPI_BOOT
+/* Try to boot an on-QSPI kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
+			   " && bootm $kernel_start" \
+			   " || run distro_bootcmd"
+#else
 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
 			   " && cp.b $kernel_start $kernel_load $kernel_size" \
 			   " && bootm $kernel_load" \
 			   " || run distro_bootcmd"
+#endif
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
@@ -391,7 +441,11 @@  unsigned long get_board_sys_clk(void);
 #define CONFIG_PHY_CORTINA
 #define CONFIG_PHYLIB
 #define	CONFIG_SYS_CORTINA_FW_IN_NOR
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_CORTINA_FW_ADDR		0x20980000
+#else
 #define CONFIG_CORTINA_FW_ADDR		0x581000000
+#endif
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 
 #define CORTINA_PHY_ADDR1	0x10