[U-Boot,1/2,v3] board: freescale: ls2080ardb: Update QIXIS code

Message ID 1492772776-30391-1-git-send-email-priyanka.jain@nxp.com
State Superseded
Headers show

Commit Message

Priyanka Jain April 21, 2017, 11:06 a.m.
Update QIXIS related code to be executed
only if CONFIG_FSL_QIXIS flag is enabled

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 board/freescale/ls2080ardb/ls2080ardb.c |   19 ++++++++++++++++---
 1 files changed, 16 insertions(+), 3 deletions(-)

Patch

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index ea05ec6..1de5058 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,8 +22,10 @@ 
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 
+#ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
+#endif
 #include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
@@ -57,12 +59,15 @@  unsigned long long get_qixis_addr(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
+#endif
 	char buf[15];
 
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
@@ -78,7 +83,7 @@  int checkboard(void)
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
+#endif
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
@@ -92,6 +97,7 @@  int checkboard(void)
 
 unsigned long get_board_sys_clk(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch (sysclk_conf & 0x0F) {
@@ -110,6 +116,7 @@  unsigned long get_board_sys_clk(void)
 	case QIXIS_SYSCLK_166:
 		return 166666666;
 	}
+#endif
 	return 66666666;
 }
 
@@ -133,6 +140,7 @@  int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int config_board_mux(int ctrl_type)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 reg5;
 
 	reg5 = QIXIS_READ(brdcfg[5]);
@@ -150,7 +158,7 @@  int config_board_mux(int ctrl_type)
 	}
 
 	QIXIS_WRITE(brdcfg[5], reg5);
-
+#endif
 	return 0;
 }
 
@@ -180,8 +188,9 @@  int board_init(void)
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#ifdef CONFIG_FSL_QIXIS
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
+#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
@@ -301,6 +310,7 @@  int ft_board_setup(void *blob, bd_t *bd)
 
 void qixis_dump_switch(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	int i, nr_of_cfgsw;
 
 	QIXIS_WRITE(cms[0], 0x00);
@@ -311,6 +321,7 @@  void qixis_dump_switch(void)
 		QIXIS_WRITE(cms[0], i);
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
+#endif
 }
 
 /*
@@ -321,6 +332,7 @@  void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -330,4 +342,5 @@  void update_spd_address(unsigned int ctrl_num,
 		else if (ctrl_num == 1 && slot == 1)
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
+#endif
 }