From patchwork Thu Apr 20 14:28:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Gonzalez X-Patchwork-Id: 752830 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3w81Xv1Pzhz9ryv for ; Fri, 21 Apr 2017 00:32:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032665AbdDTOcM (ORCPT ); Thu, 20 Apr 2017 10:32:12 -0400 Received: from mail1.bemta8.messagelabs.com ([216.82.243.206]:60264 "EHLO mail1.bemta8.messagelabs.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S946408AbdDTOcG (ORCPT ); Thu, 20 Apr 2017 10:32:06 -0400 Received: from [216.82.242.46] by server-14.bemta-8.messagelabs.com id 4B/9D-01724-066C8F85; Thu, 20 Apr 2017 14:32:00 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJIsWRWlGSWpSXmKPExsVy+LrFKt2EYz8 iDOafErHYsXQzk8WrM2vZLDY9vsZqcXnXHDaLs/OOs1kcWNrOYvHm9wt2i793/rFZHPzwhNWi 5ekMRovNm6YyO3B79M+ewuaxZt4aRo/+dZ9ZPTat6mTzeHfuHLvH5iX1Hp83yQWwR7Fm5iXlV ySwZixrmc1cMNOwYvHUi8wNjJe1uhi5OIQEljFKvJ7awN7FyMkhLGAr8fvbLDYQm03AROLm/X MsILaIgK/E338L2UAamAWOM0vc39HBDJIQEnCWWHroOFgDL5D96PBtsEEsAqoSn9fOBasRFUi QuPhnCitEjaDEyZlPwIZyCrhIXL22BKyXWUBfomnrHGYIW15i+9s5UPO1Jd5vXAzWKyGgIDF1 civzBEb+WUhGzULSPgtJ+wJG5lWMGsWpRWWpRbqGxnpJRZnpGSW5iZk5uoYGFnq5qcXFiempO YlJxXrJ+bmbGIFRUs/AwLiD8dZxl0OMkhxMSqK8anN/RAjxJeWnVGYkFmfEF5XmpBYfYpTh4F CS4LU9CpQTLEpNT61Iy8wBxitMWoKDR0mEVxckzVtckJhbnJkOkTrFqCglzmsGkhAASWSU5sG 1wVLEJUZZKWFeRgYGBiGegtSi3MwSVPlXjOIcjErCENt5MvNK4Ka/AlrMBLT4rB/Y4pJEhJRU A2Nk7tpdOtmuAlO5Xt++vzgi+12RsonHkbnc/Go34xXkd4slG3/WDZS4IuDy9zaLpN7W6IuH3 0u6OCocNf7/tKrt0JxovrN6jjcfdwmsbzwVrbL2jOszvaKlV/pW797bMKNeb8ZMZeeDYYWizC cvXv6o1OuxxOIg7w2uiRI2BhsXTt21IPKeQqYSS3FGoqEWc1FxIgAC8npVDAMAAA== X-Env-Sender: Marc_Gonzalez@sigmadesigns.com X-Msg-Ref: server-8.tower-96.messagelabs.com!1492698719!82256906!1 X-Originating-IP: [195.215.56.170] X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23598 invoked from network); 20 Apr 2017 14:32:00 -0000 Received: from 195-215-56-170-static.dk.customer.tdc.net (HELO CPH-EX1.SDESIGNS.COM) (195.215.56.170) by server-8.tower-96.messagelabs.com with AES128-SHA encrypted SMTP; 20 Apr 2017 14:32:00 -0000 Received: from [172.27.0.114] (172.27.0.114) by CPH-EX1.sdesigns.com (192.168.10.36) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 20 Apr 2017 16:31:58 +0200 Subject: [PATCH v4 1/2] PCI: Add tango MSI controller support From: Marc Gonzalez To: Marc Zyngier , Thomas Gleixner CC: Bjorn Helgaas , Robin Murphy , Lorenzo Pieralisi , Liviu Dudau , David Laight , linux-pci , Linux ARM , Thibaud Cornic , Phuong Nguyen , LKML , Mason References: Message-ID: <1f6b50c7-4887-838e-8c7d-c014d82b6d8e@sigmadesigns.com> Date: Thu, 20 Apr 2017 16:28:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:51.0) Gecko/20100101 Firefox/51.0 SeaMonkey/2.48 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [172.27.0.114] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The MSI controller in Tango supports 256 message-signaled interrupts, and a single doorbell address. Signed-off-by: Marc Gonzalez --- drivers/pci/host/pcie-tango.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) diff --git a/drivers/pci/host/pcie-tango.c b/drivers/pci/host/pcie-tango.c new file mode 100644 index 000000000000..ada8d35066ab --- /dev/null +++ b/drivers/pci/host/pcie-tango.c @@ -0,0 +1,232 @@ +#include +#include +#include +#include +#include + +#define MSI_MAX 256 + +struct tango_pcie { + DECLARE_BITMAP(bitmap, MSI_MAX); + spinlock_t lock; + void __iomem *mux; + void __iomem *msi_status; + void __iomem *msi_enable; + phys_addr_t msi_doorbell; + struct irq_domain *irq_dom; + struct irq_domain *msi_dom; + int irq; +}; + +/*** MSI CONTROLLER SUPPORT ***/ + +static void dispatch(struct tango_pcie *pcie, unsigned long status, int base) +{ + unsigned int pos, virq; + + for_each_set_bit(pos, &status, 32) { + virq = irq_find_mapping(pcie->irq_dom, base + pos); + generic_handle_irq(virq); + } +} + +static void tango_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct tango_pcie *pcie = irq_desc_get_handler_data(desc); + unsigned int status, base, pos = 0; + + chained_irq_enter(chip, desc); + + while ((pos = find_next_bit(pcie->bitmap, MSI_MAX, pos)) < MSI_MAX) { + base = round_down(pos, 32); + status = readl_relaxed(pcie->msi_status + base / 8); + dispatch(pcie, status, base); + pos = base + 32; + } + + chained_irq_exit(chip, desc); +} + +static void tango_ack(struct irq_data *data) +{ + u32 bit = BIT(data->hwirq); + struct tango_pcie *pcie = irq_data_get_irq_chip_data(data); + + writel_relaxed(bit, pcie->msi_status); +} + +static void update_msi_enable(struct irq_data *data, bool unmask) +{ + unsigned long flags; + u32 val, bit = BIT(data->hwirq % 32); + int byte_offset = (data->hwirq / 32) * 4; + struct tango_pcie *pcie = data->chip_data; + + spin_lock_irqsave(&pcie->lock, flags); + val = readl_relaxed(pcie->msi_enable + byte_offset); + val = unmask ? val | bit : val & ~bit; + writel_relaxed(val, pcie->msi_enable + byte_offset); + spin_unlock_irqrestore(&pcie->lock, flags); +} + +static void tango_mask(struct irq_data *data) +{ + update_msi_enable(data, false); +} + +static void tango_unmask(struct irq_data *data) +{ + update_msi_enable(data, true); +} + +static int tango_set_affinity(struct irq_data *data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static void tango_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct tango_pcie *pcie = irq_data_get_irq_chip_data(data); + + msg->address_lo = lower_32_bits(pcie->msi_doorbell); + msg->address_hi = upper_32_bits(pcie->msi_doorbell); + msg->data = data->hwirq; +} + +static struct irq_chip tango_chip = { + .irq_ack = tango_ack, + .irq_mask = tango_mask, + .irq_unmask = tango_unmask, + .irq_set_affinity = tango_set_affinity, + .irq_compose_msi_msg = tango_compose_msi_msg, +}; + +static void msi_ack(struct irq_data *data) +{ + irq_chip_ack_parent(data); +} + +static void msi_mask(struct irq_data *data) +{ + pci_msi_mask_irq(data); + irq_chip_mask_parent(data); +} + +static void msi_unmask(struct irq_data *data) +{ + pci_msi_unmask_irq(data); + irq_chip_unmask_parent(data); +} + +static struct irq_chip msi_chip = { + .name = "MSI", + .irq_ack = msi_ack, + .irq_mask = msi_mask, + .irq_unmask = msi_unmask, +}; + +static struct msi_domain_info msi_dom_info = { + .flags = MSI_FLAG_PCI_MSIX + | MSI_FLAG_USE_DEF_DOM_OPS + | MSI_FLAG_USE_DEF_CHIP_OPS, + .chip = &msi_chip, +}; + +static int find_free_msi(struct irq_domain *dom, unsigned int virq) +{ + unsigned int pos; + struct tango_pcie *pcie = dom->host_data; + + pos = find_first_zero_bit(pcie->bitmap, MSI_MAX); + if (pos >= MSI_MAX) + return -ENOSPC; + __set_bit(pos, pcie->bitmap); + + irq_domain_set_info(dom, virq, pos, &tango_chip, pcie, + handle_edge_irq, NULL, NULL); + + return 0; +} + +static int tango_irq_domain_alloc(struct irq_domain *dom, + unsigned int virq, unsigned int nr_irqs, void *args) +{ + int err; + unsigned long flags; + struct tango_pcie *pcie = dom->host_data; + + spin_lock_irqsave(&pcie->lock, flags); + err = find_free_msi(dom, virq); + spin_unlock_irqrestore(&pcie->lock, flags); + + return err; +} + +static void tango_irq_domain_free(struct irq_domain *dom, + unsigned int virq, unsigned int nr_irqs) +{ + unsigned long flags; + struct irq_data *data = irq_domain_get_irq_data(dom, virq); + struct tango_pcie *pcie = irq_data_get_irq_chip_data(data); + + spin_lock_irqsave(&pcie->lock, flags); + __clear_bit(data->hwirq, pcie->bitmap); + spin_unlock_irqrestore(&pcie->lock, flags); +} + +static const struct irq_domain_ops irq_dom_ops = { + .alloc = tango_irq_domain_alloc, + .free = tango_irq_domain_free, +}; + +static int tango_msi_remove(struct platform_device *pdev) +{ + struct tango_pcie *pcie = platform_get_drvdata(pdev); + + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + irq_domain_remove(pcie->msi_dom); + irq_domain_remove(pcie->irq_dom); + + return 0; +} + +static int tango_msi_probe(struct platform_device *pdev, struct tango_pcie *pcie) +{ + int i, virq; + struct irq_domain *msi_dom, *irq_dom; + struct fwnode_handle *fwnode = of_node_to_fwnode(pdev->dev.of_node); + + spin_lock_init(&pcie->lock); + for (i = 0; i < MSI_MAX / 32; ++i) + writel_relaxed(0, pcie->msi_enable + i * 4); + + irq_dom = irq_domain_create_linear(fwnode, MSI_MAX, &irq_dom_ops, pcie); + if (!irq_dom) { + pr_err("Failed to create IRQ domain\n"); + return -ENOMEM; + } + + msi_dom = pci_msi_create_irq_domain(fwnode, &msi_dom_info, irq_dom); + if (!msi_dom) { + pr_err("Failed to create MSI domain\n"); + irq_domain_remove(irq_dom); + return -ENOMEM; + } + + virq = platform_get_irq(pdev, 1); + if (virq <= 0) { + pr_err("Failed to map IRQ\n"); + irq_domain_remove(msi_dom); + irq_domain_remove(irq_dom); + return -ENXIO; + } + + pcie->irq_dom = irq_dom; + pcie->msi_dom = msi_dom; + pcie->irq = virq; + irq_set_chained_handler_and_data(virq, tango_msi_isr, pcie); + + return 0; +}