From patchwork Thu Apr 20 08:37:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 752705 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w7sln00DGz9s4s for ; Thu, 20 Apr 2017 18:41:07 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="u2NjFraE"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 75402C21DA3; Thu, 20 Apr 2017 08:41:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DABB9C21C76; Thu, 20 Apr 2017 08:40:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 932D0C21C76; Thu, 20 Apr 2017 08:40:56 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id D48DBC21C42 for ; Thu, 20 Apr 2017 08:40:55 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3K8eSXv005080; Thu, 20 Apr 2017 03:40:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1492677628; bh=jJdWTRPBQFj3jkEUxg0HcK37HWqatRj81C/jfSyJIpg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u2NjFraEHgRXSkLlSXoEf/2C5GfzO3xLJMXosPgWo1LhxxW05w6NC6556Hm7rp2Ee TnhOsuo6RLyXbAxHsFdReP/LtNofC5chXChdc5IQx21o1ZnPP4V7c0rKc83oLhRE3N ODvOTZAUI6L31OA3v3auDC6vEJQgD0xmVMUYHNlg= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3K8eNLL023787; Thu, 20 Apr 2017 03:40:23 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Thu, 20 Apr 2017 03:40:22 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3K8eJhF014775; Thu, 20 Apr 2017 03:40:20 -0500 From: Lokesh Vutla To: Tom Rini , Date: Thu, 20 Apr 2017 14:07:52 +0530 Message-ID: <20170420083752.10925-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170416044355.17629-1-lokeshvutla@ti.com> References: <20170416044355.17629-1-lokeshvutla@ti.com> MIME-Version: 1.0 Cc: Tero Kristo Subject: [U-Boot] [PATCH v2] board: dra71: Fix selection of OPPs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer Signed-off-by: Suman Anna Signed-off-by: Lokesh Vutla --- Changes since v1: - Updated efuse reg bits for OPP_HIGH as pointed out by Suman. board/ti/dra7xx/evm.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index ae2d59da43..ed0bc181cf 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -438,14 +438,18 @@ struct vcores_data dra718_volts = { * and are powered by BUCK1 of LP873X PMIC */ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = LP873X_REG_ADDR_BUCK1, .eve.pmic = &lp8733, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = LP873X_REG_ADDR_BUCK1, .iva.pmic = &lp8733, @@ -456,27 +460,44 @@ int get_voltrail_opp(int rail_offset) { int opp; - /* - * DRA71x supports only OPP_NOM. - */ - if (board_is_dra71x_evm()) - return OPP_NOM; - switch (rail_offset) { case VOLT_MPU: opp = DRA7_MPU_OPP; + /* DRA71x supports only OPP_NOM for MPU */ + if (board_is_dra71x_evm()) + opp = OPP_NOM; break; case VOLT_CORE: opp = DRA7_CORE_OPP; + /* DRA71x supports only OPP_NOM for CORE */ + if (board_is_dra71x_evm()) + opp = OPP_NOM; break; case VOLT_GPU: opp = DRA7_GPU_OPP; + /* DRA71x supports only OPP_NOM for GPU */ + if (board_is_dra71x_evm()) + opp = OPP_NOM; break; case VOLT_EVE: opp = DRA7_DSPEVE_OPP; + /* + * DRA71x does not support OPP_OD for EVE. + * If OPP_OD is selected by menuconfig, fallback + * to OPP_NOM. + */ + if (board_is_dra71x_evm() && opp == OPP_OD) + opp = OPP_NOM; break; case VOLT_IVA: opp = DRA7_IVA_OPP; + /* + * DRA71x does not support OPP_OD for IVA. + * If OPP_OD is selected by menuconfig, fallback + * to OPP_NOM. + */ + if (board_is_dra71x_evm() && opp == OPP_OD) + opp = OPP_NOM; break; default: opp = OPP_NOM;