From patchwork Thu Apr 20 07:28:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aneesh Kumar K.V" X-Patchwork-Id: 752665 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w7r9N3rDzz9s7d for ; Thu, 20 Apr 2017 17:29:44 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3w7r9N2xnQzDqKp for ; Thu, 20 Apr 2017 17:29:44 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3w7r8H2m02zDqJC for ; Thu, 20 Apr 2017 17:28:47 +1000 (AEST) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v3K7Noil024580 for ; Thu, 20 Apr 2017 03:28:36 -0400 Received: from e36.co.us.ibm.com (e36.co.us.ibm.com [32.97.110.154]) by mx0a-001b2d01.pphosted.com with ESMTP id 29x7543u4a-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 20 Apr 2017 03:28:36 -0400 Received: from localhost by e36.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 20 Apr 2017 01:28:33 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v3K7SWs59240854; Thu, 20 Apr 2017 00:28:32 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94992C6055; Thu, 20 Apr 2017 01:28:32 -0600 (MDT) Received: from skywalker.in.ibm.com (unknown [9.85.73.8]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP id 14BB9C603C; Thu, 20 Apr 2017 01:28:29 -0600 (MDT) From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, Madhavan Srinivasan , Anton Blanchard Subject: [RFC PATCH] powerpc/mm/radix: Optimize tlbiel flush Date: Thu, 20 Apr 2017 12:58:25 +0530 X-Mailer: git-send-email 2.7.4 X-TM-AS-GCONF: 00 x-cbid: 17042007-0020-0000-0000-00000BC9E8AA X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006943; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000208; SDB=6.00849972; UDB=6.00419757; IPR=6.00628602; BA=6.00005304; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015101; XFM=3.00000013; UTC=2017-04-20 07:28:35 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17042007-0021-0000-0000-00005BCFC335 Message-Id: <1492673305-29526-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-20_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1704200060 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" For a page walk cache flush, we don't need to loop with set number. The set number is ignored with RIC=1 (pwc flush). For RIC=2 (flush all), inorder to flush implementation dependent caches, we can ignore the set number. Hence we do a RIC=2 flush with set no: 0, so we do both the tlb flush for set 0 and the implementation dependent cache flushes. This is then followed with tbl flush for set 1-127 Signed-off-by: Aneesh Kumar K.V Acked-by: Anton Blanchard --- Note: not yet tested. arch/powerpc/mm/tlb-radix.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c index b68b5219cf45..b827aef38b90 100644 --- a/arch/powerpc/mm/tlb-radix.c +++ b/arch/powerpc/mm/tlb-radix.c @@ -43,12 +43,30 @@ static inline void __tlbiel_pid(unsigned long pid, int set, */ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) { - int set; + int set = 0; asm volatile("ptesync": : :"memory"); - for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) { - __tlbiel_pid(pid, set, ric); + if (ric == RIC_FLUSH_ALL) { + ric = RIC_FLUSH_TLB; + set = 1; + /* Use set 0 to flush all */ + __tlbiel_pid(pid, 0, RIC_FLUSH_ALL); } + + for (; set < POWER9_TLB_SETS_RADIX ; set++) + __tlbiel_pid(pid, set, ric); + + asm volatile("ptesync": : :"memory"); + asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); +} + +static inline void _tlbiel_pwc(unsigned long pid) +{ + asm volatile("ptesync": : :"memory"); + /* + * for PWC flush, we don't look at set number + */ + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); asm volatile("ptesync": : :"memory"); asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); } @@ -140,7 +158,7 @@ void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) pid = mm->context.id; if (pid != MMU_NO_CONTEXT) - _tlbiel_pid(pid, RIC_FLUSH_PWC); + _tlbiel_pwc(pid); preempt_enable(); } @@ -222,7 +240,7 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) if (lock_tlbie) raw_spin_unlock(&native_tlbie_lock); } else - _tlbiel_pid(pid, RIC_FLUSH_PWC); + _tlbiel_pwc(pid); no_context: preempt_enable(); }