From patchwork Wed Apr 19 09:21:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 752145 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w7GjQ2xdYz9ryZ for ; Wed, 19 Apr 2017 19:22:02 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="pZhG5zEU"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=xV8VE5FtyokJgntqM HXdeWOBQ/nYWBs5uTzkzh6b+MQuFYdzDs/nLvDuppzbD3YQGT2o9F7l5LJHzIwhx iCEXK324BUH/Xm+Qt4RY1aNkpqJYNJdDINgoE5Pw1vIbD2qs3iDZZxb2td2eJUos y3MimgL7Xq/ouDUSwhddwPxobY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=A0GJcSDgtmsHZgv/DNtiDdL yxNg=; b=pZhG5zEU/t4lFfG3FnaULJjO2w4/ADlIndSOtMnKPITE0Nc87/z2h4K tb8RV0W8gDQMjfaCIEkxyXGdA9KzLqPFpKdAS0rZQMcgZY7K8pvO/GZATsWnU8ta a2a8Nu1NmHauvBm9j3LFe/lJP00VkSxR2ahv3SbZntbe9vUClvsY= Received: (qmail 39320 invoked by alias); 19 Apr 2017 09:21:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 39304 invoked by uid 89); 19 Apr 2017 09:21:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=tied, Mode, Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Apr 2017 09:21:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F26EB16; Wed, 19 Apr 2017 02:21:50 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BEA5B3F41F; Wed, 19 Apr 2017 02:21:49 -0700 (PDT) Subject: Re: [PATCH, GCC/ARM, stage4] Set mode for success result of atomic compare and swap To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: From: Thomas Preudhomme Message-ID: <5a537560-804f-a432-31b6-6efa5e0cf026@foss.arm.com> Date: Wed, 19 Apr 2017 10:21:48 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Stage 4 ping? Best regards, Thomas On 12/04/17 09:59, Thomas Preudhomme wrote: > Hi, > > Currently atomic_compare_and_swap_1 define_insn do not have a mode > set for the destination of the set indicating the success result of the > instruction. This is because the operand can be either a CC_Z register > (for 32-bit targets) or a SI register (for 16-bit Thumb targets). This > result in lack of checking for the mode. > > This commit use a new CCSI iterator to solve this issue while avoiding > duplication of the patterns. The insn name are kept unique by using > attributes tied to the iterator (SIDI:mode and CCSI:arch) instead of > usign the builtin mode attribute. Expander arm_expand_compare_and_swap > is also adapted accordingly. > > ChangeLog entry is as follows: > > *** gcc/ChangeLog *** > > 2017-04-11 Thomas Preud'homme > > * config/arm/iterators.md (CCSI): New mode iterator. > (arch): New mode attribute. > * config/arm/sync.md (atomic_compare_and_swap_1): Rename into ... > (atomic_compare_and_swap_1): This and ... > (atomic_compare_and_swap_1): This. Use CCSI > code iterator for success result mode. > * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use > the corresponding new insn generators. > > Testing: arm-none-eabi cross-compiler built successfully for ARMv8-M > Mainline and Baseline without the lack of destination mode warning in > sync.md. Testsuite show no regression. > > Is this ok for stage4? > > Best regards, > > Thomas diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b24143e32e2f100000f3b150f7ed0df4fabb3cc8..cf628714507efd2b5a5ab5de97ef32fd45987d1f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28190,17 +28190,32 @@ arm_expand_compare_and_swap (rtx operands[]) gcc_unreachable (); } - switch (mode) + if (TARGET_THUMB1) { - case QImode: gen = gen_atomic_compare_and_swapqi_1; break; - case HImode: gen = gen_atomic_compare_and_swaphi_1; break; - case SImode: gen = gen_atomic_compare_and_swapsi_1; break; - case DImode: gen = gen_atomic_compare_and_swapdi_1; break; - default: - gcc_unreachable (); + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swapt1qi_1; break; + case HImode: gen = gen_atomic_compare_and_swapt1hi_1; break; + case SImode: gen = gen_atomic_compare_and_swapt1si_1; break; + case DImode: gen = gen_atomic_compare_and_swapt1di_1; break; + default: + gcc_unreachable (); + } + } + else + { + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swap32qi_1; break; + case HImode: gen = gen_atomic_compare_and_swap32hi_1; break; + case SImode: gen = gen_atomic_compare_and_swap32si_1; break; + case DImode: gen = gen_atomic_compare_and_swap32di_1; break; + default: + gcc_unreachable (); + } } - bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CCmode, CC_REGNUM); + bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CC_Zmode, CC_REGNUM); emit_insn (gen (bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f)); if (mode == QImode || mode == HImode) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index e2e588688eb04c158d1c146bca12d84cfb5ff130..48992879a8eecc66eba913c2b9a7c5989c5c7bc6 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -45,6 +45,9 @@ ;; A list of the 32bit and 64bit integer modes (define_mode_iterator SIDI [SI DI]) +;; A list of atomic compare and swap success return modes +(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) + ;; A list of modes which the VFP unit can handle (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) @@ -411,6 +414,10 @@ ;; Mode attributes ;;---------------------------------------------------------------------------- +;; Determine name of atomic compare and swap from success result mode. This +;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. +(define_mode_attr arch [(CC_Z "32") (SI "t1")]) + ;; Determine element size suffix from vector mode. (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 1f91b7364d5689145a10bbb193d54a0677b2fd36..b4b4f2e6815e7c31c9874c19af31e908107e6a62 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -191,9 +191,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (zero_extend:SI (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory @@ -223,9 +223,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2)