[v2,1/5] phb4: Expand and clean up register definitions

Submitted by Russell Currey on April 19, 2017, 5:14 a.m.

Details

Message ID 20170419051408.26335-2-ruscur@russell.cc
State Accepted
Headers show

Commit Message

Russell Currey April 19, 2017, 5:14 a.m.
Add some missing register definitions, delete some duplicates and put things
in order.

Signed-off-by: Russell Currey <ruscur@russell.cc>
---
 include/phb4-regs.h | 130 ++++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 121 insertions(+), 9 deletions(-)

Patch hide | download patch | download mbox

diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 48953e40..54809490 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -121,6 +121,7 @@ 
 #define PHB_ETU_ERR_SUMMARY		0x2c8
 #define PHB_INT_NOTIFY_ADDR		0x300
 #define PHB_INT_NOTIFY_INDEX		0x308
+
 #define PHB_VERSION			0x800
 #define PHB_CTRLR			0x810
 #define   PHB_CTRLR_IRQ_PGSZ_64K	PPC_BIT(11)
@@ -135,6 +136,9 @@ 
 #define     TVT_8_PER_PE		3
 #define     TVT_16_PER_PE		4
 #define   PHB_CTRLR_DMA_RD_SPACING	PPC_BITMASK(28,31)
+#define PHB_AIB_FENCE_CTRL		0x860
+#define PHB_TCE_TAG_ENABLE		0x868
+#define PHB_TCE_WATERMARK		0x870
 #define PHB_TIMEOUT_CTRL1		0x878
 #define PHB_TIMEOUT_CTRL2		0x880
 #define PHB_Q_DMA_R			0x888
@@ -144,19 +148,111 @@ 
 #define   PHB_Q_DMA_R_MMIO_RESP_STATUS	PPC_BIT(5)
 #define   PHB_Q_DMA_R_TCE_RESP_STATUS	PPC_BIT(6)
 #define   PHB_Q_DMA_R_TCE_KILL_STATUS	PPC_BIT(7)
+#define PHB_TCE_TAG_STATUS		0x908
+
+/* FIR & Error registers - identical to PHB3 */
+#define PHB_LEM_FIR_ACCUM		0xc00
+#define PHB_LEM_FIR_AND_MASK		0xc08
+#define PHB_LEM_FIR_OR_MASK		0xc10
+#define PHB_LEM_ERROR_MASK		0xc18
+#define PHB_LEM_ERROR_AND_MASK		0xc20
+#define PHB_LEM_ERROR_OR_MASK		0xc28
+#define PHB_LEM_ACTION0			0xc30
+#define PHB_LEM_ACTION1			0xc38
+#define PHB_LEM_WOF			0xc40
+#define PHB_ERR_STATUS			0xc80
+#define PHB_ERR1_STATUS			0xc88
+#define PHB_ERR_INJECT			0xc90
+#define PHB_ERR_LEM_ENABLE		0xc98
+#define PHB_ERR_IRQ_ENABLE		0xca0
+#define PHB_ERR_FREEZE_ENABLE		0xca8
+#define PHB_ERR_AIB_FENCE_ENABLE	0xcb0
+#define PHB_ERR_LOG_0			0xcc0
+#define PHB_ERR_LOG_1			0xcc8
+#define PHB_ERR_STATUS_MASK		0xcd0
+#define PHB_ERR1_STATUS_MASK		0xcd8
+
+/*
+ * Instead of MMIO outbound, inboundA and inboundB in PHB3,
+ * PHB4 has TXE (outbound), RXE_ARB, RXE_MRG and RXE_TCE.
+ */
+
+#define PHB_TXE_ERR_STATUS			0xd00
+#define PHB_TXE_ERR1_STATUS			0xd08
+#define PHB_TXE_ERR_INJECT			0xd10
+#define PHB_TXE_ERR_LEM_ENABLE			0xd18
+#define PHB_TXE_ERR_IRQ_ENABLE			0xd20
+#define PHB_TXE_ERR_FREEZE_ENABLE		0xd28
+#define PHB_TXE_ERR_AIB_FENCE_ENABLE		0xd30
+#define PHB_TXE_ERR_LOG_0			0xd40
+#define PHB_TXE_ERR_LOG_1			0xd48
+#define PHB_TXE_ERR_STATUS_MASK			0xd50
+#define PHB_TXE_ERR1_STATUS_MASK		0xd58
+
+#define PHB_RXE_ARB_ERR_STATUS			0xd80
+#define PHB_RXE_ARB_ERR1_STATUS			0xd88
+#define PHB_RXE_ARB_ERR_INJECT			0xd90
+#define PHB_RXE_ARB_ERR_LEM_ENABLE      	0xd98
+#define PHB_RXE_ARB_ERR_IRQ_ENABLE		0xda0
+#define PHB_RXE_ARB_ERR_FREEZE_ENABLE		0xda8
+#define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE	0xdb0
+#define PHB_RXE_ARB_ERR_LOG_0			0xdc0
+#define PHB_RXE_ARB_ERR_LOG_1			0xdc8
+#define PHB_RXE_ARB_ERR_STATUS_MASK		0xdd0
+#define PHB_RXE_ARB_ERR1_STATUS_MASK		0xdd8
+
+#define PHB_RXE_MRG_ERR_STATUS			0xe00
+#define PHB_RXE_MRG_ERR1_STATUS			0xe08
+#define PHB_RXE_MRG_ERR_INJECT			0xe10
+#define PHB_RXE_MRG_ERR_LEM_ENABLE		0xe18
+#define PHB_RXE_MRG_ERR_IRQ_ENABLE		0xe20
+#define PHB_RXE_MRG_ERR_FREEZE_ENABLE		0xe28
+#define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE	0xe30
+#define PHB_RXE_MRG_ERR_LOG_0			0xe40
+#define PHB_RXE_MRG_ERR_LOG_1			0xe48
+#define PHB_RXE_MRG_ERR_STATUS_MASK		0xe50
+#define PHB_RXE_MRG_ERR1_STATUS_MASK		0xe58
+
+#define PHB_RXE_TCE_ERR_STATUS			0xe80
+#define PHB_RXE_TCE_ERR1_STATUS			0xe88
+#define PHB_RXE_TCE_ERR_INJECT			0xe90
+#define PHB_RXE_TCE_ERR_LEM_ENABLE		0xe98
+#define PHB_RXE_TCE_ERR_IRQ_ENABLE		0xea0
+#define PHB_RXE_TCE_ERR_FREEZE_ENABLE		0xea8
+#define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE	0xeb0
+#define PHB_RXE_TCE_ERR_LOG_0			0xec0
+#define PHB_RXE_TCE_ERR_LOG_1			0xec8
+#define PHB_RXE_TCE_ERR_STATUS_MASK		0xed0
+#define PHB_RXE_TCE_ERR1_STATUS_MASK		0xed8
 
 /* Performance monitor & Debug registers */
-#define PHB_TRACE_CONTROL		0xf80
-#define PHB_PERFMON_CONFIG		0xf88
-#define PHB_PERFMON_CTR0		0xf90
-#define PHB_PERFMON_CTR1		0xf98
-#define PHB_PERFMON_CTR2		0xfa0
-#define PHB_PERFMON_CTR3		0xfa8
+#define PHB_TRACE_CONTROL			0xf80
+#define PHB_PERFMON_CONFIG			0xf88
+#define PHB_PERFMON_CTR0			0xf90
+#define PHB_PERFMON_CTR1			0xf98
+#define PHB_PERFMON_CTR2			0xfa0
+#define PHB_PERFMON_CTR3			0xfa8
 
 // FIXME add more here
-#define PHB_RC_CONFIG_BASE		0x1000
-
-#define PHB_PBL_TIMEOUT_CTRL		0x1810
+#define PHB_RC_CONFIG_BASE			0x1000
+
+/* PHB4 REGB registers */
+#define PHB_PBL_CONTROL				0x1800
+#define PHB_PBL_TIMEOUT_CTRL			0x1810
+#define PHB_PBL_NPTAG_ENABLE			0x1820
+#define PHB_PBL_NBW_CMP_MASK			0x1830
+#define PHB_PBL_SYS_LINK_INIT			0x1838
+#define PHB_PBL_BUF_STATUS			0x1840
+#define PHB_PBL_ERR_STATUS			0x1900
+#define PHB_PBL_ERR1_STATUS			0x1908
+#define PHB_PBL_ERR_INJECT			0x1910
+#define PHB_PBL_ERR_INF_ENABLE			0x1920
+#define PHB_PBL_ERR_ERC_ENABLE			0x1928
+#define PHB_PBL_ERR_FAT_ENABLE			0x1930
+#define PHB_PBL_ERR_LOG_0			0x1940
+#define PHB_PBL_ERR_LOG_1			0x1948
+#define PHB_PBL_ERR_STATUS_MASK			0x1950
+#define PHB_PBL_ERR1_STATUS_MASK		0x1958
 
 // FIXME add more here
 #define PHB_PCIE_SCR			0x1A00
@@ -178,6 +274,11 @@ 
 #define	  PHB_PCIE_DLP_TL_LINKACT	PPC_BIT(23)
 #define   PHB_PCIE_DLP_INBAND_PRESENCE  PPC_BIT(19)
 
+#define PHB_PCIE_DLP_ERRLOG1		0x1AA0
+#define PHB_PCIE_DLP_ERRLOG2		0x1AA8
+#define PHB_PCIE_DLP_ERR_STATUS		0x1AB0
+#define PHB_PCIE_DLP_ERR_COUNTERS	0x1AB8
+
 #define PHB_PCIE_LANE_EQ_CNTL0		0x1AD0
 #define PHB_PCIE_LANE_EQ_CNTL1		0x1AD8
 #define PHB_PCIE_LANE_EQ_CNTL2		0x1AE0
@@ -187,6 +288,17 @@ 
 #define PHB_PCIE_LANE_EQ_CNTL22		0x1B00 /* DD1 only */
 #define PHB_PCIE_LANE_EQ_CNTL23		0x1B08 /* DD1 only */
 
+#define PHB_REGB_ERR_STATUS		0x1C00
+#define PHB_REGB_ERR1_STATUS		0x1C08
+#define PHB_REGB_ERR_INJECT		0x1C10
+#define PHB_REGB_ERR_INF_ENABLE		0x1C20
+#define PHB_REGB_ERR_ERC_ENABLE		0x1C28
+#define PHB_REGB_ERR_FAT_ENABLE		0x1C30
+#define PHB_REGB_ERR_LOG_0		0x1C40
+#define PHB_REGB_ERR_LOG_1		0x1C48
+#define PHB_REGB_ERR_STATUS_MASK	0x1C50
+#define PHB_REGB_ERR1_STATUS_MASK	0x1C58
+
 /*
  * PHB4 xscom address defines
  */