| Message ID | 20170418191220.3166-2-npiggin@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 8d1b48ef580097e111c2644e6fc6041b9784d218 |
| Headers | show |
On Tue, 2017-04-18 at 19:12:16 UTC, Nicholas Piggin wrote: > The XIVE enablement patches set LPES0 on POWER9 host. This bit sets > external interrupts to guest delivery mode that uses SRR[01]. The host's > EE interrupt handler expects HSRR[01] (for earlier CPUs). which is fine > because XIVE is configured not to deliver EE to the host (HVI is used > instead) so this should never be executed. > > However a bug in interrupt controller code or odd configuration of > mambo/systemsim could result in the host getting EE. Keeping EE delivery > mode matching the host handler prevents strange crashes due to using > the wrong exception registers. > > When running in guest mode and getting EE, the guest LPCR will be > loaded by KVM which contains the LPES0 bit. > > Fixes: 08a1e650cc ("powerpc: Fixup LPCR:PECE and HEIC setting on POWER9") > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/8d1b48ef580097e111c2644e6fc604 cheers
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 7013ae3d1675..1fce4ddd2e6c 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -107,7 +107,7 @@ _GLOBAL(__setup_cpu_power9) or r3, r3, r4 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR) andc r3, r3, r4 - li r4,(LPCR_LPES0 >> LPCR_LPES_SH) + li r4,0 /* LPES = 0 */ bl __init_LPCR bl __init_HFSCR bl __init_tlb_power9 @@ -131,7 +131,7 @@ _GLOBAL(__restore_cpu_power9) or r3, r3, r4 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR) andc r3, r3, r4 - li r4,(LPCR_LPES0 >> LPCR_LPES_SH) + li r4,0 /* LPES = 0 */ bl __init_LPCR bl __init_HFSCR bl __init_tlb_power9
The XIVE enablement patches set LPES0 on POWER9 host. This bit sets external interrupts to guest delivery mode that uses SRR[01]. The host's EE interrupt handler expects HSRR[01] (for earlier CPUs). which is fine because XIVE is configured not to deliver EE to the host (HVI is used instead) so this should never be executed. However a bug in interrupt controller code or odd configuration of mambo/systemsim could result in the host getting EE. Keeping EE delivery mode matching the host handler prevents strange crashes due to using the wrong exception registers. When running in guest mode and getting EE, the guest LPCR will be loaded by KVM which contains the LPES0 bit. Fixes: 08a1e650cc ("powerpc: Fixup LPCR:PECE and HEIC setting on POWER9") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- arch/powerpc/kernel/cpu_setup_power.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)