| Message ID | 1492103757-22375-2-git-send-email-ludovic.Barre@st.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Hi all, Rob, is this version ok for you? If so, I can take it into the github/spi-nor tree. Best regards, Cyrille Le 13/04/2017 à 19:15, Ludovic Barre a écrit : > From: Ludovic Barre <ludovic.barre@st.com> > > This patch adds documentation of device tree bindings for the STM32 > QSPI controller. > > Signed-off-by: Ludovic Barre <ludovic.barre@st.com> > --- > .../devicetree/bindings/mtd/stm32-quadspi.txt | 43 ++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/stm32-quadspi.txt > > diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt > new file mode 100644 > index 0000000..ddd18c1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt > @@ -0,0 +1,43 @@ > +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) > + > +Required properties: > +- compatible: should be "st,stm32f469-qspi" > +- reg: the first contains the register location and length. > + the second contains the memory mapping address and length > +- reg-names: should contain the reg names "qspi" "qspi_mm" > +- interrupts: should contain the interrupt for the device > +- clocks: the phandle of the clock needed by the QSPI controller > +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer > + > +Optional properties: > +- resets: must contain the phandle to the reset controller. > + > +A spi flash must be a child of the nor_flash node and could have some > +properties. Also see jedec,spi-nor.txt. > + > +Required properties: > +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) > +- spi-max-frequency: max frequency of spi bus > + > +Optional property: > +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description > + > +Example: > + > +qspi: spi@a0001000 { > + compatible = "st,stm32f469-qspi"; > + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; > + reg-names = "qspi", "qspi_mm"; > + interrupts = <91>; > + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; > + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_qspi0>; > + > + flash@0 { > + reg = <0>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; > + ... > + }; > +}; > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Apr 13, 2017 at 07:15:56PM +0200, Ludovic Barre wrote: > From: Ludovic Barre <ludovic.barre@st.com> > > This patch adds documentation of device tree bindings for the STM32 > QSPI controller. > > Signed-off-by: Ludovic Barre <ludovic.barre@st.com> > --- > .../devicetree/bindings/mtd/stm32-quadspi.txt | 43 ++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/stm32-quadspi.txt Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sun, Apr 16, 2017 at 06:53:06PM +0200, Cyrille Pitchen wrote: > Hi all, > > Rob, is this version ok for you? If so, I can take it into the > github/spi-nor tree. I see this was missing from your pull request. Rob has since acked, so... Applied to l2-mtd.git -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Le 02/05/2017 à 03:09, Brian Norris a écrit : > On Sun, Apr 16, 2017 at 06:53:06PM +0200, Cyrille Pitchen wrote: >> Hi all, >> >> Rob, is this version ok for you? If so, I can take it into the >> github/spi-nor tree. > > I see this was missing from your pull request. Rob has since acked, > so... > > Applied to l2-mtd.git > Indeed, thanks! > ______________________________________________________ > Linux MTD discussion mailing list > http://lists.infradead.org/mailman/listinfo/linux-mtd/ > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt new file mode 100644 index 0000000..ddd18c1 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt @@ -0,0 +1,43 @@ +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) + +Required properties: +- compatible: should be "st,stm32f469-qspi" +- reg: the first contains the register location and length. + the second contains the memory mapping address and length +- reg-names: should contain the reg names "qspi" "qspi_mm" +- interrupts: should contain the interrupt for the device +- clocks: the phandle of the clock needed by the QSPI controller +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer + +Optional properties: +- resets: must contain the phandle to the reset controller. + +A spi flash must be a child of the nor_flash node and could have some +properties. Also see jedec,spi-nor.txt. + +Required properties: +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) +- spi-max-frequency: max frequency of spi bus + +Optional property: +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description + +Example: + +qspi: spi@a0001000 { + compatible = "st,stm32f469-qspi"; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <91>; + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + flash@0 { + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + ... + }; +};