pinctrl: sh-pfc: r8a7794: add R8A7745 support

Message ID 20170412204839.408318444@cogentembedded.com
State New
Headers show

Commit Message

Sergei Shtylyov April 12, 2017, 8:48 p.m.
Renesas  RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
however  it doesn't have several automotive specific peripherals.
Annotate all the items that only exist on the R-Car SoCs and only
supply the pin groups/functions existing on a given SoC (that required
splitting of the AVB function)...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'
repo plus  R8A7794 PFC fix and R8A7743 PFC support patch...

 drivers/pinctrl/sh-pfc/Kconfig       |    5 
 drivers/pinctrl/sh-pfc/Makefile      |    1 
 drivers/pinctrl/sh-pfc/core.c        |    6 
 drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 1970 ++++++++++++++++++++---------------
 drivers/pinctrl/sh-pfc/sh_pfc.h      |    1 
 5 files changed, 1139 insertions(+), 844 deletions(-)


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Comments

Sergei Shtylyov April 12, 2017, 8:53 p.m. | #1
Apparently forgot to run checkpatch.pl on this patch before sending... :-<
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Patch

Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Kconfig
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
@@ -39,6 +39,11 @@  config PINCTRL_PFC_R8A7743
 	depends on ARCH_R8A7743
 	select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7745
+        def_bool y
+        depends on ARCH_R8A7745
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7778
 	def_bool y
 	depends on ARCH_R8A7778
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Makefile
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
@@ -4,6 +4,7 @@  obj-$(CONFIG_PINCTRL_PFC_EMEV2)	+= pfc-e
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7743)	+= pfc-r8a7791.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7745)	+= pfc-r8a7794.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7778)	+= pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)	+= pfc-r8a7779.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7790)	+= pfc-r8a7790.o
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/core.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
@@ -491,6 +491,12 @@  static const struct of_device_id sh_pfc_
 		.data = &r8a7743_pinmux_info,
 	},
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+        {
+                .compatible = "renesas,pfc-r8a7745",
+                .data = &r8a7745_pinmux_info,
+        },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 	{
 		.compatible = "renesas,pfc-r8a7778",
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -1,9 +1,9 @@ 
 /*
- * r8a7794 processor support - PFC hardware block.
+ * r8a7794/r8a7745 processor support - PFC hardware block.
  *
  * Copyright (C) 2014-2015 Renesas Electronics Corporation
  * Copyright (C) 2015 Renesas Solutions Corp.
- * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
+ * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2
@@ -110,10 +110,12 @@  enum {
 	FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
 	FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 	FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
-	FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
-	FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
-	FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
-	FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
+	FN_SCIFA1_SCK, FN_TANS1 /* R8A7794 only */, FN_PWM2_C, FN_TCLK2_B,
+	FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B,
+	FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B,
+	FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD,
+	FN_A3, FN_SCIFB0_SCK, FN_A4, FN_SCIFB0_TXD,
+	FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 	FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 
 	/* IPSR2 */
@@ -123,77 +125,139 @@  enum {
 	FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
 	FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 	FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
-	FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
-	FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
-	FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
-	FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
-	FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
+	FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN /* R8A7794 only */,
+	FN_VSP /* R8A7794 only */, FN_CAN_CLK_C, FN_TPUTO2_B,
+	FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
+	FN_AVB_AVTP_CAPTURE_B /* R8A7794 only */,
+	FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
+	FN_AVB_AVTP_MATCH_B /* R8A7794 only */,
+	FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, FN_MOUT0 /* R8A7794 only */,
+	FN_A20, FN_SPCLK, FN_MOUT1 /* R8A7794 only */,
 
 	/* IPSR3 */
-	FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
-	FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
-	FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
+	FN_A21, FN_MOSI_IO0, FN_MOUT2 /* R8A7794 only */,
+	FN_A22, FN_MISO_IO1, FN_MOUT5 /* R8A7794 only */, FN_ATADIR1_N,
+	FN_A23, FN_IO2, FN_MOUT6 /* R8A7794 only */, FN_ATAWR1_N,
+	FN_A24, FN_IO3, FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N,
+	FN_CS0_N, FN_VI1_DATA8,
 	FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
-	FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
-	FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
-	FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
-	FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
-	FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
-	FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
-	FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
-	FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
+	FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
+	FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B /* R8A7794 only */,
+	FN_RIF0_SYNC /* R8A7794 only */, FN_TPUTO3, FN_SCIFB2_TXD,
+	FN_SDATA_B /* R8A7794 only */,
+	FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C,
+	FN_TS_SCK_B /* R8A7794 only */, FN_RIF0_CLK /* R8A7794 only */,
+	FN_BPFCLK /* R8A7794 only */, FN_SCIFB2_SCK,
+	FN_MDATA_B /* R8A7794 only */,
+	FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E,
+	FN_TS_SDEN_B /* R8A7794 only */, FN_RIF0_D0 /* R8A7794 only */,
+	FN_FMCLK /* R8A7794 only */, FN_SCIFB2_CTS_N,
+	FN_SCKZ_B /* R8A7794 only */,
+	FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
+	FN_TS_SPSYNC_B /* R8A7794 only */, FN_RIF0_D1 /* R8A7794 only */,
+	FN_FMIN /* R8A7794 only */, FN_SCIFB2_RTS_N,
+	FN_STM_N_B /* R8A7794 only */,
+	FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
+	FN_MTS_N_B /* R8A7794 only */,
 	FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
 
 	/* IPSR4 */
-	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
-	FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
-	FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
-	FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
-	FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
-	FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
-	FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
-	FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
-	FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
-	FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
-	FN_LCDOUT12, FN_CC50_STATE12,
+	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0 /* R8A7794 only */,
+	FN_DU0_DR0, FN_LCDOUT16 /* R8A7794 only */, FN_SCIF5_RXD_C,
+	FN_I2C2_SCL_D, FN_CC50_STATE0 /* R8A7794 only */,
+	FN_DU0_DR1, FN_LCDOUT17 /* R8A7794 only */, FN_SCIF5_TXD_C,
+	FN_I2C2_SDA_D, FN_CC50_STATE1 /* R8A7794 only */,
+	FN_DU0_DR2, FN_LCDOUT18 /* R8A7794 only */,
+	FN_CC50_STATE2 /* R8A7794 only */,
+	FN_DU0_DR3, FN_LCDOUT19 /* R8A7794 only */,
+	FN_CC50_STATE3 /* R8A7794 only */,
+	FN_DU0_DR4, FN_LCDOUT20 /* R8A7794 only */,
+	FN_CC50_STATE4 /* R8A7794 only */,
+	FN_DU0_DR5, FN_LCDOUT21 /* R8A7794 only */,
+	FN_CC50_STATE5 /* R8A7794 only */,
+	FN_DU0_DR6, FN_LCDOUT22 /* R8A7794 only */,
+	FN_CC50_STATE6 /* R8A7794 only */,
+	FN_DU0_DR7, FN_LCDOUT23 /* R8A7794 only */,
+	FN_CC50_STATE7 /* R8A7794 only */,
+	FN_DU0_DG0, FN_LCDOUT8 /* R8A7794 only */, FN_SCIFA0_RXD_C,
+	FN_I2C3_SCL_D, FN_CC50_STATE8 /* R8A7794 only */,
+	FN_DU0_DG1, FN_LCDOUT9 /* R8A7794 only */, FN_SCIFA0_TXD_C,
+	FN_I2C3_SDA_D, FN_CC50_STATE9 /* R8A7794 only */,
+	FN_DU0_DG2, FN_LCDOUT10 /* R8A7794 only */,
+	FN_CC50_STATE10 /* R8A7794 only */,
+	FN_DU0_DG3, FN_LCDOUT11 /* R8A7794 only */,
+	FN_CC50_STATE11 /* R8A7794 only */,
+	FN_DU0_DG4, FN_LCDOUT12 /* R8A7794 only */,
+	FN_CC50_STATE12 /* R8A7794 only */,
 
 	/* IPSR5 */
-	FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
-	FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
-	FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
-	FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
-	FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
-	FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
-	FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
-	FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
-	FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
-	FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
-	FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
+	FN_DU0_DG5, FN_LCDOUT13 /* R8A7794 only */,
+	FN_CC50_STATE13 /* R8A7794 only */,
+	FN_DU0_DG6, FN_LCDOUT14 /* R8A7794 only */,
+	FN_CC50_STATE14 /* R8A7794 only */,
+	FN_DU0_DG7, FN_LCDOUT15 /* R8A7794 only */,
+	FN_CC50_STATE15 /* R8A7794 only */,
+	FN_DU0_DB0, FN_LCDOUT0 /* R8A7794 only */, FN_SCIFA4_RXD_C,
+	FN_I2C4_SCL_D, FN_CAN0_RX_C, FN_CC50_STATE16 /* R8A7794 only */,
+	FN_DU0_DB1, FN_LCDOUT1 /* R8A7794 only */, FN_SCIFA4_TXD_C,
+	FN_I2C4_SDA_D, FN_CAN0_TX_C, FN_CC50_STATE17 /* R8A7794 only */,
+	FN_DU0_DB2, FN_LCDOUT2 /* R8A7794 only */,
+	FN_CC50_STATE18 /* R8A7794 only */,
+	FN_DU0_DB3, FN_LCDOUT3 /* R8A7794 only */,
+	FN_CC50_STATE19 /* R8A7794 only */,
+	FN_DU0_DB4, FN_LCDOUT4 /* R8A7794 only */,
+	FN_CC50_STATE20 /* R8A7794 only */,
+	FN_DU0_DB5, FN_LCDOUT5 /* R8A7794 only */,
+	FN_CC50_STATE21 /* R8A7794 only */,
+	FN_DU0_DB6, FN_LCDOUT6 /* R8A7794 only */,
+	FN_CC50_STATE22 /* R8A7794 only */,
+	FN_DU0_DB7, FN_LCDOUT7 /* R8A7794 only */,
+	FN_CC50_STATE23 /* R8A7794 only */,
+	FN_DU0_DOTCLKIN, FN_QSTVA_QVS /* R8A7794 only */,
+	FN_CC50_STATE24 /* R8A7794 only */,
+	FN_DU0_DOTCLKOUT0, FN_QCLK /* R8A7794 only */,
+	FN_CC50_STATE25 /* R8A7794 only */,
+	FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE /* R8A7794 only */,
+	FN_CC50_STATE26 /* R8A7794 only */,
+	FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS /* R8A7794 only */,
+	FN_CC50_STATE27 /* R8A7794 only */,
 
 	/* IPSR6 */
-	FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
-	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
-	FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
-	FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
+	FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE /* R8A7794 only */,
+	FN_CC50_STATE28 /* R8A7794 only */,
+	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE /* R8A7794 only */,
+	FN_CC50_STATE29 /* R8A7794 only */,
+	FN_DU0_DISP, FN_QPOLA /* R8A7794 only */,
+	FN_CC50_STATE30 /* R8A7794 only */,
+	FN_DU0_CDE, FN_QPOLB /* R8A7794 only */,
+	FN_CC50_STATE31 /* R8A7794 only */,
+	FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
 	FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
 	FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
 	FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
-	FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
-	FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
-	FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
-	FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
+	FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+	FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C,
+	FN_IETX_C /* R8A7794 only */, FN_AVB_RXD7,
+	FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C,
+	FN_IECLK_C /* R8A7794 only */, FN_AVB_RX_ER,
+	FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C,
+	FN_IERX_C /* R8A7794 only */, FN_AVB_COL, FN_VI0_VSYNC_N,
 	FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
 	FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
-	FN_ADIDATA, FN_AD_DI,
+	FN_ADIDATA /* R8A7794 only */, FN_AD_DI /* R8A7794 only */,
 
 	/* IPSR7 */
 	FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
-	FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
-	FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
-	FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
+	FN_ADICS_SAMP /* R8A7794 only */, FN_AD_DO /* R8A7794 only */,
+	FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
+	FN_ADICLK /* R8A7794 only */, FN_AD_CLK /* R8A7794 only */,
+	FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
+	FN_ADICHS0 /* R8A7794 only */, FN_AD_NCS_N /* R8A7794 only */,
 	FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
-	FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
-	FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
+	FN_ADICHS1 /* R8A7794 only */,
+	FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
+	FN_ADICHS2 /* R8A7794 only */,
+	FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
 	FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
 	FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
 	FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
@@ -213,127 +277,188 @@  enum {
 	FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 	FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
 	FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
-	FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
-	FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
-	FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
-	FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+	FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B /* R8A7794 only */,
+	FN_TS_SDATA_D /* R8A7794 only */, FN_TPUTO1_B,
+	FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+	FN_RIF1_CLK_B /* R8A7794 only */, FN_TS_SCK_D /* R8A7794 only */,
+	FN_BPFCLK_C /* R8A7794 only */,
+	FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+	FN_RIF1_D0_B /* R8A7794 only */, FN_TS_SDEN_D /* R8A7794 only */,
+	FN_FMCLK_C /* R8A7794 only */, FN_RDS_CLK /* R8A7794 only */,
 
 	/* IPSR9 */
-	FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
-	FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
-	FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
-	FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
-	FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
-	FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
-	FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
-	FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
-	FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
-	FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
-	FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
-	FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
-	FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
-	FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
+	FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
+	FN_RIF1_D1_B /* R8A7794 only */, FN_TS_SPSYNC_D /* R8A7794 only */,
+	FN_FMIN_C /* R8A7794 only */, FN_RDS_DATA /* R8A7794 only */,
+	FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA /* R8A7794 only */, FN_DU1_DR4,
+	FN_RIF1_SYNC /* R8A7794 only */, FN_TPUTO1_C,
+	FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK /* R8A7794 only */, FN_DU1_DR5,
+	FN_RIF1_CLK /* R8A7794 only */, FN_BPFCLK_B /* R8A7794 only */,
+	FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN /* R8A7794 only */,
+	FN_DU1_DR6, FN_RIF1_D0 /* R8A7794 only */,
+	FN_FMCLK_B /* R8A7794 only */, FN_RDS_CLK_B /* R8A7794 only */,
+	FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC /* R8A7794 only */,
+	FN_DU1_DR7, FN_RIF1_D1 /* R8A7794 only */, FN_FMIN_B /* R8A7794 only */,
+	FN_RDS_DATA_B /* R8A7794 only */,
+	FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX,
+	FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, FN_HSCIF1_HSCK, FN_PWM2,
+	FN_IETX /* R8A7794 only */, FN_DU1_DG2, FN_REMOCON_B /* R8A7794 only */,
+	FN_SPEEDIN_B /* R8A7794 only */, FN_VSP_B /* R8A7794 only */,
+	FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK /* R8A7794 only */,
+	FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER /* R8A7794 only */,
+	FN_CC50_STATE32 /* R8A7794 only */,
+	FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX /* R8A7794 only */,
+	FN_DU1_DG4, FN_SSI_WS1_B, FN_CAN_STEP0 /* R8A7794 only */,
+	FN_CC50_STATE33 /* R8A7794 only */,
+	FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
+	FN_CAN_TXCLK /* R8A7794 only */, FN_CC50_STATE34 /* R8A7794 only */,
 
 	/* IPSR10 */
-	FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
-	FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
-	FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
-	FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
-	FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
-	FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
-	FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
-	FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
-	FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
-	FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
-	FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
-	FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
-	FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
-	FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
-	FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
-	FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
+	FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
+	FN_CAN_DEBUGOUT0 /* R8A7794 only */, FN_CC50_STATE35 /* R8A7794 only */,
+	FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
+	FN_CAN_DEBUGOUT1 /* R8A7794 only */, FN_CC50_STATE36 /* R8A7794 only */,
+	FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
+	FN_USB0_EXTLP /* R8A7794 only */, FN_CAN_DEBUGOUT2 /* R8A7794 only */,
+	FN_CC50_STATE37 /* R8A7794 only */,
+	FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
+	FN_USB0_OVC1 /* R8A7794 only */, FN_CAN_DEBUGOUT3 /* R8A7794 only */,
+	FN_CC50_STATE38 /* R8A7794 only */,
+	FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
+	FN_USB0_IDIN /* R8A7794 only */, FN_CAN_DEBUGOUT4 /* R8A7794 only */,
+	FN_CC50_STATE39 /* R8A7794 only */, FN_SCIF3_SCK, FN_IRQ2,
+	FN_BPFCLK_D /* R8A7794 only */, FN_DU1_DB3, FN_SSI_SDATA9_B,
+	FN_TANS2 /* R8A7794 only */, FN_CAN_DEBUGOUT5 /* R8A7794 only */,
+	FN_CC50_OSCOUT /* R8A7794 only */,
+	FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D /* R8A7794 only */, FN_DU1_DB4,
+	FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6 /* R8A7794 only */,
+	FN_RDS_CLK_C /* R8A7794 only */,
+	FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D /* R8A7794 only */, FN_DU1_DB5,
+	FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7 /* R8A7794 only */,
+	FN_RDS_DATA_C /* R8A7794 only */,
+	FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
+	FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8 /* R8A7794 only */,
+	FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+	FN_CAN_DEBUGOUT9 /* R8A7794 only */,
+	FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
+	FN_CAN_DEBUGOUT10 /* R8A7794 only */,
 
 	/* IPSR11 */
 	FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
-	FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
-	FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
-	FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
-	FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
-	FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
-	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
-	FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
-	FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
-	FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
-	FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
-	FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
-	FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
-	FN_ADICLK_B, FN_AD_CLK_B,
+	FN_CAN_DEBUGOUT11 /* R8A7794 only */,
+	FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+	FN_CAN_DEBUGOUT12 /* R8A7794 only */, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
+	FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13 /* R8A7794 only */,
+	FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+	FN_CAN_DEBUGOUT14 /* R8A7794 only */,
+	FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15 /* R8A7794 only */,
+	FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
+	FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
+	FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
+	FN_PCMOE_N /* R8A7794 only */,
+	FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D,
+	FN_ADIDATA_B /* R8A7794 only */, FN_AD_DI_B /* R8A7794 only */,
+	FN_PCMWE_N /* R8A7794 only */,
+	FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
+	FN_ADICS_SAMP_B /* R8A7794 only */, FN_AD_DO_B /* R8A7794 only */,
+	FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
+	FN_ADICLK_B /* R8A7794 only */, FN_AD_CLK_B /* R8A7794 only */,
 
 	/* IPSR12 */
-	FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
-	FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
-	FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
-	FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
-	FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
-	FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
-	FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
-	FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
-	FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
-	FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
-	FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
-	FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
-	FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
-	FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,
+	FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C,
+	FN_ADICHS0_B /* R8A7794 only */, FN_AD_NCS_N_B /* R8A7794 only */,
+	FN_DREQ1_N_B,
+	FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C,
+	FN_ADICHS1_B /* R8A7794 only */, FN_CAN1_RX_C, FN_DACK1_B,
+	FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C,
+	FN_ADICHS2_B /* R8A7794 only */, FN_CAN1_TX_C, FN_DREQ2_N,
+	FN_SSI_SCK4, FN_MLB_CLK /* R8A7794 only */,
+	FN_IETX_B /* R8A7794 only */, FN_IRD_TX /* R8A7794 only */,
+	FN_SSI_WS4, FN_MLB_SIG /* R8A7794 only */,
+	FN_IECLK_B /* R8A7794 only */, FN_IRD_RX /* R8A7794 only */,
+	FN_SSI_SDATA4, FN_MLB_DAT /* R8A7794 only */,
+	FN_IERX_B /* R8A7794 only */, FN_IRD_SCK /* R8A7794 only */,
+	FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
+	FN_REMOCON /* R8A7794 only */, FN_DACK2, FN_ETH_MDIO_B,
+	FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
+	FN_AVB_AVTP_CAPTURE /* R8A7794 only */, FN_ETH_CRS_DV_B,
+	FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
+	FN_AVB_AVTP_MATCH /* R8A7794 only */, FN_ETH_RX_ER_B,
+	FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA /* R8A7794 only */,
+	FN_VI1_DATA1, FN_ATAWR0_N, FN_ETH_RXD0_B,
+	FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA /* R8A7794 only */,
+	FN_ATAG0_N, FN_ETH_RXD1_B,
 
 	/* IPSR13 */
-	FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
-	FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
-	FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
-	FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
-	FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
-	FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
-	FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
-	FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
-	FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
+	FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
+	FN_SCKZ /* R8A7794 only */, FN_ATACS00_N, FN_ETH_LINK_B,
+	FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
+	FN_STM_N /* R8A7794 only */, FN_ATACS10_N, FN_ETH_REFCLK_B,
+	FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
+	FN_MTS_N /* R8A7794 only */, FN_EX_WAIT1, FN_ETH_TXD1_B,
+	FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
+	FN_ETH_TX_EN_B,
+	FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
+	FN_ATADIR0_N, FN_ETH_MAGIC_B,
+	FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
+	FN_TS_SDATA_C /* R8A7794 only */, FN_RIF0_SYNC_B /* R8A7794 only */,
+	FN_ETH_TXD0_B,
 	FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
-	FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
-	FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
-	FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
-	FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
-	FN_FMIN_E, FN_RDS_DATA_D,
+	FN_TS_SCK_C /* R8A7794 only */, FN_RIF0_CLK_B /* R8A7794 only */,
+	FN_BPFCLK_E /* R8A7794 only */, FN_ETH_MDC_B,
+	FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
+	FN_TS_SDEN_C /* R8A7794 only */, FN_RIF0_D0_B /* R8A7794 only */,
+	FN_FMCLK_E /* R8A7794 only */, FN_RDS_CLK_D /* R8A7794 only */,
+	FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
+	FN_TS_SPSYNC_C /* R8A7794 only */, FN_RIF0_D1_B /* R8A7794 only */,
+	FN_FMIN_E /* R8A7794 only */, FN_RDS_DATA_D /* R8A7794 only */,
 
 	/* MOD_SEL */
 	FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
-	FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
-	FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
-	FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
-	FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
-	FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
-	FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
+	/* R8A7794 only */ FN_SEL_ADI_0, FN_SEL_ADI_1,
+	FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+	/* R8A7794 only */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2,
+	FN_SEL_DARC_3, FN_SEL_DARC_4,
+	/* R8A7794 only */ FN_SEL_DR0_0, FN_SEL_DR0_1,
+	/* R8A7794 only */ FN_SEL_DR1_0, FN_SEL_DR1_1,
+	/* R8A7794 only */ FN_SEL_DR2_0, FN_SEL_DR2_1,
+	/* R8A7794 only */ FN_SEL_DR3_0, FN_SEL_DR3_1,
+	FN_SEL_ETH_0, FN_SEL_ETH_1,
+	/* R8A7794 only */ FN_SEL_FSN_0, FN_SEL_FSN_1,
+	FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
 	FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
 	FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
 	FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
 	FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 	FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
 	FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
-	FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
+	FN_SEL_IIC00_2, FN_SEL_IIC00_3,
+	/* R8A7794 only */ FN_SEL_AVB_0, FN_SEL_AVB_1,
 
 	/* MOD_SEL2 */
-	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
-	FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
-	FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
-	FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
-	FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
-	FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
-	FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
-	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
-	FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
-	FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
-	FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
-	FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-	FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
-	FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
-	FN_SEL_RDS_2, FN_SEL_RDS_3,
+	/* R8A7794 only */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_IIC01_0,	FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
+	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
+	FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
+	/* R8A7794 only */ FN_SEL_RCN_0, FN_SEL_RCN_1,
+	/* R8A7794 only */ FN_SEL_RSP_0, FN_SEL_RSP_1,
+	FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
+	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
+	/* R8A7794 only */ FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+	FN_SEL_TMU_0, FN_SEL_TMU_1,
+	/* R8A7794 only */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2,
+	FN_SEL_TSIF0_3,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+	/* R8A7794 only */ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+	FN_SEL_RDS_3,
 
 	/* MOD_SEL3 */
 	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
@@ -378,7 +503,8 @@  enum {
 	HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 	D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 	D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
-	D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
+	D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK /* R8A7794 only */, PWM2_C_MARK,
+	TCLK2_B_MARK,
 	D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
 	IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
 	SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
@@ -393,89 +519,145 @@  enum {
 	A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
 	HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
 	HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
-	HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
-	TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
-	CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
-	SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
-	MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
-	SPCLK_MARK, MOUT1_MARK,
+	HSCIF0_HSCK_B_MARK, SPEEDIN_MARK /* R8A7794 only */,
+	VSP_MARK /* R8A7794 only */, CAN_CLK_C_MARK, TPUTO2_B_MARK,
+	A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
+	AVB_AVTP_CAPTURE_B_MARK /* R8A7794 only */,
+	A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
+	AVB_AVTP_MATCH_B_MARK /* R8A7794 only */,
+	A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
+	MOUT0_MARK /* R8A7794 only */,
+	A20_MARK, SPCLK_MARK, MOUT1_MARK /* R8A7794 only */,
 
 	/* IPSR3 */
-	A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
-	MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
-	ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
-	ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
-	VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
-	TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
-	PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
-	TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
-	SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
-	BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
-	SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
-	FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
-	SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
-	FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
-	PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
-	ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
+	A21_MARK, MOSI_IO0_MARK, MOUT2_MARK /* R8A7794 only */,
+	A22_MARK, MISO_IO1_MARK, MOUT5_MARK /* R8A7794 only */, ATADIR1_N_MARK,
+	A23_MARK, IO2_MARK, MOUT6_MARK /* R8A7794 only */, ATAWR1_N_MARK,
+	A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, ATARD1_N_MARK,
+	CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, VI1_DATA9_MARK,
+	EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, TPUTO3_B_MARK,
+	SCIFB2_RXD_MARK, VI1_DATA11_MARK,
+	EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK,
+	TS_SDATA_B_MARK /* R8A7794 only */, RIF0_SYNC_MARK /* R8A7794 only */,
+	TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK /* R8A7794 only */,
+	EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK,
+	TS_SCK_B_MARK /* R8A7794 only */, RIF0_CLK_MARK /* R8A7794 only */,
+	BPFCLK_MARK /* R8A7794 only */, SCIFB2_SCK_MARK,
+	MDATA_B_MARK /* R8A7794 only */,
+	EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK,
+	TS_SDEN_B_MARK /* R8A7794 only */, RIF0_D0_MARK /* R8A7794 only */,
+	FMCLK_MARK /* R8A7794 only */, SCIFB2_CTS_N_MARK,
+	SCKZ_B_MARK /* R8A7794 only */,
+	EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK,
+	TS_SPSYNC_B_MARK /* R8A7794 only */, RIF0_D1_MARK /* R8A7794 only */,
+	FMIN_MARK /* R8A7794 only */, SCIFB2_RTS_N_MARK,
+	STM_N_B_MARK /* R8A7794 only */, BS_N_MARK, DRACK0_MARK, PWM1_C_MARK,
+	TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK /* R8A7794 only */,
+	RD_N_MARK, ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
 
 	/* IPSR4 */
-	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
-	DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
-	CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
-	I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
-	CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
-	DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
-	LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
-	CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
-	DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
-	CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
-	I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
-	CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
-	DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
+	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
+	PWMFSW0_MARK /* R8A7794 only */,
+	DU0_DR0_MARK, LCDOUT16_MARK /* R8A7794 only */, SCIF5_RXD_C_MARK,
+	I2C2_SCL_D_MARK, CC50_STATE0_MARK /* R8A7794 only */,
+	DU0_DR1_MARK, LCDOUT17_MARK /* R8A7794 only */, SCIF5_TXD_C_MARK,
+	I2C2_SDA_D_MARK, CC50_STATE1_MARK /* R8A7794 only */,
+	DU0_DR2_MARK, LCDOUT18_MARK /* R8A7794 only */,
+	CC50_STATE2_MARK /* R8A7794 only */,
+	DU0_DR3_MARK, LCDOUT19_MARK /* R8A7794 only */,
+	CC50_STATE3_MARK /* R8A7794 only */,
+	DU0_DR4_MARK, LCDOUT20_MARK /* R8A7794 only */,
+	CC50_STATE4_MARK /* R8A7794 only */,
+	DU0_DR5_MARK, LCDOUT21_MARK /* R8A7794 only */,
+	CC50_STATE5_MARK /* R8A7794 only */,
+	DU0_DR6_MARK, LCDOUT22_MARK /* R8A7794 only */,
+	CC50_STATE6_MARK /* R8A7794 only */,
+	DU0_DR7_MARK, LCDOUT23_MARK /* R8A7794 only */,
+	CC50_STATE7_MARK /* R8A7794 only */,
+	DU0_DG0_MARK, LCDOUT8_MARK /* R8A7794 only */, SCIFA0_RXD_C_MARK,
+	I2C3_SCL_D_MARK, CC50_STATE8_MARK /* R8A7794 only */,
+	DU0_DG1_MARK, LCDOUT9_MARK /* R8A7794 only */, SCIFA0_TXD_C_MARK,
+	I2C3_SDA_D_MARK, CC50_STATE9_MARK /* R8A7794 only */,
+	DU0_DG2_MARK, LCDOUT10_MARK /* R8A7794 only */,
+	CC50_STATE10_MARK /* R8A7794 only */,
+	DU0_DG3_MARK, LCDOUT11_MARK /* R8A7794 only */,
+	CC50_STATE11_MARK /* R8A7794 only */,
+	DU0_DG4_MARK, LCDOUT12_MARK /* R8A7794 only */,
+	CC50_STATE12_MARK /* R8A7794 only */,
 
 	/* IPSR5 */
-	DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
-	LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
-	CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
-	I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
-	LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
-	CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
-	DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
-	LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
-	CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
-	DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
-	QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
-	QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
-	CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
-	CC50_STATE27_MARK,
+	DU0_DG5_MARK, LCDOUT13_MARK /* R8A7794 only */,
+	CC50_STATE13_MARK /* R8A7794 only */,
+	DU0_DG6_MARK, LCDOUT14_MARK /* R8A7794 only */,
+	CC50_STATE14_MARK /* R8A7794 only */,
+	DU0_DG7_MARK, LCDOUT15_MARK /* R8A7794 only */,
+	CC50_STATE15_MARK /* R8A7794 only */,
+	DU0_DB0_MARK, LCDOUT0_MARK /* R8A7794 only */, SCIFA4_RXD_C_MARK,
+	I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK /* R8A7794 only */,
+	DU0_DB1_MARK, LCDOUT1_MARK /* R8A7794 only */, SCIFA4_TXD_C_MARK,
+	I2C4_SDA_D_MARK, CAN0_TX_C_MARK, CC50_STATE17_MARK /* R8A7794 only */,
+	DU0_DB2_MARK, LCDOUT2_MARK /* R8A7794 only */,
+	CC50_STATE18_MARK /* R8A7794 only */,
+	DU0_DB3_MARK, LCDOUT3_MARK /* R8A7794 only */,
+	CC50_STATE19_MARK /* R8A7794 only */,
+	DU0_DB4_MARK, LCDOUT4_MARK /* R8A7794 only */,
+	CC50_STATE20_MARK /* R8A7794 only */,
+	DU0_DB5_MARK, LCDOUT5_MARK /* R8A7794 only */,
+	CC50_STATE21_MARK /* R8A7794 only */,
+	DU0_DB6_MARK, LCDOUT6_MARK /* R8A7794 only */,
+	CC50_STATE22_MARK /* R8A7794 only */,
+	DU0_DB7_MARK, LCDOUT7_MARK /* R8A7794 only */,
+	CC50_STATE23_MARK /* R8A7794 only */,
+	DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK /* R8A7794 only */,
+	CC50_STATE24_MARK /* R8A7794 only */,
+	DU0_DOTCLKOUT0_MARK, QCLK_MARK /* R8A7794 only */,
+	CC50_STATE25_MARK /* R8A7794 only */,
+	DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK /* R8A7794 only */,
+	CC50_STATE26_MARK /* R8A7794 only */,
+	DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK /* R8A7794 only */,
+	CC50_STATE27_MARK /* R8A7794 only */,
 
 	/* IPSR6 */
-	DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
-	DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
-	CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
+	DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK /* R8A7794 only */,
+	CC50_STATE28_MARK /* R8A7794 only */,
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK /* R8A7794 only */,
+	CC50_STATE29_MARK /* R8A7794 only */,
+	DU0_DISP_MARK, QPOLA_MARK /* R8A7794 only */,
+	CC50_STATE30_MARK /* R8A7794 only */,
+	DU0_CDE_MARK, QPOLB_MARK /* R8A7794 only */,
+	CC50_STATE31_MARK /* R8A7794 only */,
+	VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
 	AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 	VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
 	AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 	VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
-	AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
-	I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
-	VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
-	AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
-	IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
-	I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
-	VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
-	ADIDATA_MARK, AD_DI_MARK,
+	AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
+	VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK,
+	IETX_C_MARK /* R8A7794 only */, AVB_RXD7_MARK,
+	VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK,
+	IECLK_C_MARK /* R8A7794 only */, AVB_RX_ER_MARK,
+	VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
+	IERX_C_MARK /* R8A7794 only */, AVB_COL_MARK,
+	VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
+	AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
+	ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK,
+	AVB_TX_CLK_MARK, ADIDATA_MARK /* R8A7794 only */,
+	AD_DI_MARK /* R8A7794 only */,
 
 	/* IPSR7 */
 	ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
-	AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
-	MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
-	AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
-	CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
+	AVB_TXD0_MARK, ADICS_SAMP_MARK /* R8A7794 only */,
+	AD_DO_MARK /* R8A7794 only */,
+	ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
+	AVB_TXD1_MARK, ADICLK_MARK /* R8A7794 only */,
+	AD_CLK_MARK /* R8A7794 only */,
+	ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
+	AVB_TXD2_MARK, ADICHS0_MARK /* R8A7794 only */,
+	AD_NCS_N_MARK /* R8A7794 only */,
 	ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
-	AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
-	MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
+	AVB_TXD3_MARK, ADICHS1_MARK /* R8A7794 only */,
+	ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
+	AVB_TXD4_MARK, ADICHS2_MARK /* R8A7794 only */,
 	ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 	SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
 	IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
@@ -499,102 +681,158 @@  enum {
 	AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 	SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 	CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
-	DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
-	I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
-	TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
-	I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
-	FMCLK_C_MARK, RDS_CLK_MARK,
+	DU1_DR0_MARK, RIF1_SYNC_B_MARK /* R8A7794 only */,
+	TS_SDATA_D_MARK /* R8A7794 only */, TPUTO1_B_MARK,
+	I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK,
+	RIF1_CLK_B_MARK /* R8A7794 only */, TS_SCK_D_MARK /* R8A7794 only */,
+	BPFCLK_C_MARK /* R8A7794 only */,
+	MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
+	RIF1_D0_B_MARK /* R8A7794 only */, TS_SDEN_D_MARK /* R8A7794 only */,
+	FMCLK_C_MARK /* R8A7794 only */, RDS_CLK_MARK /* R8A7794 only */,
 
 	/* IPSR9 */
 	MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
-	RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
-	MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
-	TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
-	RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
-	TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
-	MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
-	RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
-	I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
-	I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
-	PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
-	VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
-	DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
-	CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
-	DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
+	RIF1_D1_B_MARK /* R8A7794 only */, TS_SPSYNC_D_MARK /* R8A7794 only */,
+	FMIN_C_MARK /* R8A7794 only */, RDS_DATA_MARK /* R8A7794 only */,
+	MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK /* R8A7794 only */,
+	DU1_DR4_MARK, RIF1_SYNC_MARK /* R8A7794 only */, TPUTO1_C_MARK,
+	MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK /* R8A7794 only */,
+	DU1_DR5_MARK, RIF1_CLK_MARK /* R8A7794 only */,
+	BPFCLK_B_MARK /* R8A7794 only */,
+	MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK /* R8A7794 only */,
+	DU1_DR6_MARK, RIF1_D0_MARK /* R8A7794 only */,
+	FMCLK_B_MARK /* R8A7794 only */, RDS_CLK_B_MARK /* R8A7794 only */,
+	MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK /* R8A7794 only */,
+	DU1_DR7_MARK, RIF1_D1_MARK /* R8A7794 only */,
+	FMIN_B_MARK /* R8A7794 only */, RDS_DATA_B_MARK /* R8A7794 only */,
+	HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
+	HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
+	HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK /* R8A7794 only */, DU1_DG2_MARK,
+	REMOCON_B_MARK /* R8A7794 only */, SPEEDIN_B_MARK /* R8A7794 only */,
+	VSP_B_MARK /* R8A7794 only */,
+	HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK /* R8A7794 only */,
+	DU1_DG3_MARK, SSI_SCK1_B_MARK,
+	CAN_DEBUG_HW_TRIGGER_MARK /* R8A7794 only */,
+	CC50_STATE32_MARK /* R8A7794 only */,
+	HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK /* R8A7794 only */,
+	DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK /* R8A7794 only */,
+	CC50_STATE33_MARK /* R8A7794 only */,
 	SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
-	CAN_TXCLK_MARK, CC50_STATE34_MARK,
+	CAN_TXCLK_MARK /* R8A7794 only */, CC50_STATE34_MARK /* R8A7794 only */,
 
 	/* IPSR10 */
 	SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
-	CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
-	DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
+	CAN_DEBUGOUT0_MARK /* R8A7794 only */,
+	CC50_STATE35_MARK /* R8A7794 only */,
+	SCIF1_TXD_MARK, IIC0_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
+	CAN_DEBUGOUT1_MARK /* R8A7794 only */,
+	CC50_STATE36_MARK /* R8A7794 only */,
 	SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
-	USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
-	IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
-	CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
-	DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
-	CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
-	DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
-	CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
-	DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
-	RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
-	DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
-	RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
-	AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
-	SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
-	SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
+	USB0_EXTLP_MARK /* R8A7794 only */,
+	CAN_DEBUGOUT2_MARK /* R8A7794 only */,
+	CC50_STATE37_MARK /* R8A7794 only */,
+	SCIF2_TXD_MARK, IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
+	USB0_OVC1_MARK /* R8A7794 only */,
+	CAN_DEBUGOUT3_MARK /* R8A7794 only */,
+	CC50_STATE38_MARK /* R8A7794 only */,
+	SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
+	USB0_IDIN_MARK /* R8A7794 only */,
+	CAN_DEBUGOUT4_MARK /* R8A7794 only */,
+	CC50_STATE39_MARK /* R8A7794 only */,
+	SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK /* R8A7794 only */,
+	DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK /* R8A7794 only */,
+	CAN_DEBUGOUT5_MARK /* R8A7794 only */,
+	CC50_OSCOUT_MARK /* R8A7794 only */,
+	SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK /* R8A7794 only */,
+	DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
+	CAN_DEBUGOUT6_MARK /* R8A7794 only */,
+	RDS_CLK_C_MARK /* R8A7794 only */,
+	SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK /* R8A7794 only */,
+	DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
+	CAN_DEBUGOUT7_MARK /* R8A7794 only */,
+	RDS_DATA_C_MARK /* R8A7794 only */,
+	I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
+	SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK /* R8A7794 only */,
+	I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
+	CAN_DEBUGOUT9_MARK /* R8A7794 only */,
+	SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
+	CAN_DEBUGOUT10_MARK /* R8A7794 only */,
 
 	/* IPSR11 */
 	SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
-	CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
-	DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
-	SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
+	CAN_DEBUGOUT11_MARK /* R8A7794 only */,
+	SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
+	CAN_DEBUGOUT12_MARK /* R8A7794 only */,
+	SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+	CAN_DEBUGOUT13_MARK /* R8A7794 only */,
 	SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
-	DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
-	SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-	CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
-	DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
-	DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
-	AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
-	MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
-	PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
-	ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
-	PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
+	DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK /* R8A7794 only */,
+	SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
+	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+	CAN_DEBUGOUT15_MARK /* R8A7794 only */,
+	SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, DU1_DISP_MARK,
+	SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, DU1_CDE_MARK,
+	SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
+	CAN_CLK_D_MARK, PCMOE_N_MARK /* R8A7794 only */,
+	SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK,
+	ADIDATA_B_MARK /* R8A7794 only */, AD_DI_B_MARK /* R8A7794 only */,
+	PCMWE_N_MARK /* R8A7794 only */,
+	SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
+	ADICS_SAMP_B_MARK /* R8A7794 only */, AD_DO_B_MARK /* R8A7794 only */,
+	SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK,
+	ADICLK_B_MARK /* R8A7794 only */, AD_CLK_B_MARK /* R8A7794 only */,
 
 	/* IPSR12 */
-	SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
-	AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
-	SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
-	SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
-	CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
-	IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
-	SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
-	SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
-	DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
-	IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
-	ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
-	VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
-	SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
-	ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
-	VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK,
+	SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK,
+	ADICHS0_B_MARK /* R8A7794 only */, AD_NCS_N_B_MARK /* R8A7794 only */,
+	DREQ1_N_B_MARK,
+	SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK,
+	ADICHS1_B_MARK /* R8A7794 only */, CAN1_RX_C_MARK, DACK1_B_MARK,
+	SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK,
+	ADICHS2_B_MARK /* R8A7794 only */, CAN1_TX_C_MARK, DREQ2_N_MARK,
+	SSI_SCK4_MARK, MLB_CLK_MARK /* R8A7794 only */,
+	IETX_B_MARK /* R8A7794 only */, IRD_TX_MARK /* R8A7794 only */,
+	SSI_WS4_MARK, MLB_SIG_MARK /* R8A7794 only */,
+	IECLK_B_MARK /* R8A7794 only */, IRD_RX_MARK,
+	SSI_SDATA4_MARK, MLB_DAT_MARK /* R8A7794 only */,
+	IERX_B_MARK /* R8A7794 only */, IRD_SCK_MARK /* R8A7794 only */,
+	SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK,
+	REMOCON_MARK /* R8A7794 only */, DACK2_MARK, ETH_MDIO_B_MARK,
+	SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC1_SCL_C_MARK, VI1_CLK_MARK,
+	CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK /* R8A7794 only */,
+	ETH_CRS_DV_B_MARK,
+	SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, VI1_DATA0_MARK,
+	CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK /* R8A7794 only */,
+	ETH_RX_ER_B_MARK,
+	SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK,
+	SDATA_MARK /* R8A7794 only */, ATAWR0_N_MARK, ETH_RXD0_B_MARK,
+	SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK,
+	MDATA_MARK /* R8A7794 only */, ATAG0_N_MARK, ETH_RXD1_B_MARK,
 
 	/* IPSR13 */
 	SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
-	SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
-	HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
-	ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
-	PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
-	ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
-	VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
-	SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
-	ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
-	VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
+	SCKZ_MARK /* R8A7794 only */, ATACS00_N_MARK, ETH_LINK_B_MARK,
+	SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
+	VI1_DATA4_MARK, STM_N_MARK /* R8A7794 only */, ATACS10_N_MARK,
+	ETH_REFCLK_B_MARK,
+	SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
+	MTS_N_MARK /* R8A7794 only */, EX_WAIT1_MARK, ETH_TXD1_B_MARK,
+	SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
+	ATARD0_N_MARK, ETH_TX_EN_B_MARK,
+	SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
+	ATADIR0_N_MARK,	ETH_MAGIC_B_MARK,
+	AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
+	TS_SDATA_C_MARK /* R8A7794 only */, RIF0_SYNC_B_MARK /* R8A7794 only */,
+	ETH_TXD0_B_MARK,
 	AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
-	TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
+	TS_SCK_C_MARK /* R8A7794 only */, RIF0_CLK_B_MARK /* R8A7794 only */,
+	BPFCLK_E_MARK /* R8A7794 only */, ETH_MDC_B_MARK,
 	AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
-	TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
+	TS_SDEN_C_MARK /* R8A7794 only */, RIF0_D0_B_MARK /* R8A7794 only */,
+	FMCLK_E_MARK /* R8A7794 only */, RDS_CLK_D_MARK /* R8A7794 only */,
 	AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
-	TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
+	TS_SPSYNC_C_MARK /* R8A7794 only */, RIF0_D1_B_MARK /* R8A7794 only */,
+	FMIN_E_MARK /* R8A7794 only */, RDS_DATA_D_MARK /* R8A7794 only */,
 	PINMUX_MARK_END,
 };
 
@@ -700,7 +938,7 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 	PINMUX_IPSR_GPSR(IP1_17_15, D13),
 	PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
-	PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
+	PINMUX_IPSR_GPSR(IP1_17_15, TANS1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 	PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 	PINMUX_IPSR_GPSR(IP1_19_18, D14),
@@ -760,40 +998,40 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP2_20_18, A16),
 	PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 	PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
-	PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
+	PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 	PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 	PINMUX_IPSR_GPSR(IP2_23_21, A17),
 	PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 	PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 	PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
-	PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
+	PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),/* R8A7794 */
 	PINMUX_IPSR_GPSR(IP2_26_24, A18),
 	PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 	PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 	PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
-	PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
+	PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), /* R8A7794 */
 	PINMUX_IPSR_GPSR(IP2_29_27, A19),
 	PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 	PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 	PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
-	PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
+	PINMUX_IPSR_GPSR(IP2_29_27, MOUT0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP2_31_30, A20),
 	PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
-	PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
+	PINMUX_IPSR_GPSR(IP2_29_27, MOUT1), /* R8A7794 only */
 
 	/* IPSR3 */
 	PINMUX_IPSR_GPSR(IP3_1_0, A21),
 	PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
-	PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
+	PINMUX_IPSR_GPSR(IP3_1_0, MOUT2), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_3_2, A22),
 	PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
-	PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
+	PINMUX_IPSR_GPSR(IP3_3_2, MOUT5), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 	PINMUX_IPSR_GPSR(IP3_5_4, A23),
 	PINMUX_IPSR_GPSR(IP3_5_4, IO2),
-	PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
+	PINMUX_IPSR_GPSR(IP3_5_4, MOUT6), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 	PINMUX_IPSR_GPSR(IP3_7_6, A24),
 	PINMUX_IPSR_GPSR(IP3_7_6, IO3),
@@ -814,41 +1052,41 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 	PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 	PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
+	PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 	PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
-	PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
+	PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 	PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 	PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
-	PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
+	PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
-	PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
+	PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 	PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 	PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
-	PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
-	PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
+	PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
-	PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
+	PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 	PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 	PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
-	PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
-	PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
+	PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), /* R8A7794 */
+	PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
-	PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
+	PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 	PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 	PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 	PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 	PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
-	PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
+	PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP3_30, RD_N),
 	PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 	PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
@@ -858,121 +1096,121 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 	PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 	PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
+	PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
-	PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
+	PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 	PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
-	PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
+	PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
-	PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
+	PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 	PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
-	PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
+	PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
-	PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
-	PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
+	PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
-	PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
-	PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
+	PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
-	PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
-	PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
+	PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
-	PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
-	PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
+	PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
-	PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
-	PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
+	PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
-	PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
-	PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
+	PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
-	PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
+	PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 	PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
-	PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
+	PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
-	PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
+	PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 	PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
-	PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
+	PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
-	PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
-	PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
+	PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
-	PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
-	PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
+	PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
-	PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
-	PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
+	PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12), /* R8A7794 only */
 
 	/* IPSR5 */
 	PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
-	PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
-	PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
+	PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
-	PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
-	PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
+	PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
-	PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
-	PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
+	PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
-	PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
+	PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 	PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 	PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
+	PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
-	PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
+	PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 	PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 	PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
+	PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
-	PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
-	PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
+	PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
-	PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
-	PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
+	PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
-	PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
-	PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
+	PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
-	PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
-	PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
+	PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
-	PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
-	PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
+	PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
-	PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
-	PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
+	PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
-	PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
+	PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
-	PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
+	PINMUX_IPSR_GPSR(IP5_27_26, QCLK), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
-	PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
+	PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
+	PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27), /* R8A7794 only */
 
 	/* IPSR6 */
 	PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
+	PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
+	PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
-	PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
-	PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
+	PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
-	PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
-	PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
+	PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 	PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 	PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
@@ -994,17 +1232,17 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
 	PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
 	PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
-	PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
+	PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
 	PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
 	PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
 	PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
-	PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
 	PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
 	PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
 	PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
-	PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
+	PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
 	PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
 	PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
@@ -1016,8 +1254,8 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
 	PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
 	PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
-	PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
+	PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0), /* R8A7794 only */
 
 	/* IPSR7 */
 	PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
@@ -1025,34 +1263,34 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
 	PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
 	PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
-	PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
+	PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
 	PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
 	PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
 	PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
 	PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
-	PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
+	PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
 	PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
 	PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
 	PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
 	PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
-	PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
+	PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
 	PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
 	PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
 	PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
 	PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
-	PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
+	PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
 	PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
 	PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
 	PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
 	PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
-	PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
+	PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
 	PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
 	PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
@@ -1136,60 +1374,60 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
 	PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
 	PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
-	PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
-	PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
 	PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
 	PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
 	PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
 	PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
-	PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
-	PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+	PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
 	PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
 	PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
 	PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
-	PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
-	PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
-	PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
+	PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0), /* R8A7794 only */
 
 	/* IPSR9 */
 	PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
 	PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
 	PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
 	PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
-	PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
-	PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
-	PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
+	PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
 	PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
-	PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
+	PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
-	PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
+	PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
 	PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
 	PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
-	PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
+	PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
-	PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
-	PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
+	PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
 	PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
-	PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
+	PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
-	PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
-	PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
-	PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
+	PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
 	PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
-	PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
+	PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
-	PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
-	PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
-	PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
+	PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
 	PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
 	PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
@@ -1200,132 +1438,132 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
 	PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
 	PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
-	PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
+	PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
-	PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
-	PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
-	PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
+	PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
 	PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
-	PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
+	PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
 	PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
-	PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
+	PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
 	PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
-	PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
+	PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
 	PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
-	PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
+	PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
 	PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
 	PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
 	PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
-	PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
+	PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34), /* R8A7794 only */
 
 	/* IPSR10 */
 	PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
 	PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
 	PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
 	PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
-	PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
+	PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
 	PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
 	PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
 	PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
-	PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
+	PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
 	PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
 	PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
 	PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
-	PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
-	PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
+	PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
 	PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
 	PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
 	PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
-	PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
-	PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
+	PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
 	PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
 	PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
 	PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
-	PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
-	PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
+	PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
 	PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
-	PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
+	PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
 	PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
-	PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
-	PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
+	PINMUX_IPSR_GPSR(IP10_17_15, TANS2), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
 	PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
-	PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
+	PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
 	PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
 	PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
-	PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
+	PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
 	PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
 	PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
-	PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
+	PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
 	PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
 	PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
-	PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
-	PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
+	PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
 	PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
 	PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
 	PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
 	PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
-	PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
+	PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
 	PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
 	PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
 	PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
-	PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
+	PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
 	PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
 	PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
+	PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10), /* R8A7794 only */
 
 	/* IPSR11 */
 	PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
 	PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
 	PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
 	PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
+	PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
 	PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
 	PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
 	PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
-	PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
+	PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
 	PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
 	PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
+	PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
 	PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
 	PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
 	PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
+	PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
 	PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
 	PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
 	PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
+	PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
 	PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
 	PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
@@ -1339,60 +1577,60 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
 	PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
 	PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
-	PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
+	PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
 	PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
 	PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
-	PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
+	PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
 	PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
 	PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
+	PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), /* R8A7794 */
+	PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
 	PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
 	PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
-	PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
+	PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1), /* R8A7794 only */
 
 	/* IPSR12 */
 	PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
 	PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
 	PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
+	PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
 	PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
 	PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
 	PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
+	PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
 	PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
 	PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
 	PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
 	PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
+	PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
 	PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
 	PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
-	PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
+	PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
-	PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
+	PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
-	PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
+	PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), /* R8A7794 only */
+	PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
 	PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
 	PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
 	PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
-	PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
+	PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
 	PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
@@ -1400,25 +1638,25 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
 	PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
 	PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
+	PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), /* R8A7794 */
 	PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
 	PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
 	PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
 	PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
 	PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
+	PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), /* R8A7794 */
 	PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
 	PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
 	PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
-	PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
+	PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
 	PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
 	PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
 	PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
-	PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
+	PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
 	PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
 
@@ -1427,21 +1665,21 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
 	PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
 	PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
-	PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
+	PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
 	PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
 	PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
 	PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
 	PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
-	PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
+	PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
 	PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
 	PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
 	PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
 	PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
-	PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
+	PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0), /* R8A7794 only */
 	PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
 	PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
@@ -1460,33 +1698,33 @@  static const u16 pinmux_data[] = {
 	PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
 	PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
 	PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
-	PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
+	PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), /* R8A7794 */
+	PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
 	PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
 	PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
 	PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
-	PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
-	PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
+	PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
 	PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
 	PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
 	PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
 	PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
-	PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
-	PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
+	PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3), /* R8A7794 only */
 	PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
 	PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
 	PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
 	PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
-	PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
-	PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
+	PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), /* R8A7794 */
+	PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), /* R8A7794 only */
+	PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3), /* R8A7794 only */
 };
 
 static const struct sh_pfc_pin pinmux_pins[] = {
@@ -1660,6 +1898,7 @@  static const unsigned int avb_gmii_mux[]
 	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 	AVB_COL_MARK,
 };
+/* - AVB AVTP (R8A7794 only) ------------------------------------------------ */
 static const unsigned int avb_avtp_capture_pins[] = {
 	RCAR_GP_PIN(5, 11),
 };
@@ -3515,275 +3754,282 @@  static const unsigned int vin1_clk_mux[]
 	VI1_CLK_MARK,
 };
 
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clka),
-	SH_PFC_PIN_GROUP(audio_clka_b),
-	SH_PFC_PIN_GROUP(audio_clka_c),
-	SH_PFC_PIN_GROUP(audio_clka_d),
-	SH_PFC_PIN_GROUP(audio_clkb),
-	SH_PFC_PIN_GROUP(audio_clkb_b),
-	SH_PFC_PIN_GROUP(audio_clkb_c),
-	SH_PFC_PIN_GROUP(audio_clkc),
-	SH_PFC_PIN_GROUP(audio_clkc_b),
-	SH_PFC_PIN_GROUP(audio_clkc_c),
-	SH_PFC_PIN_GROUP(audio_clkout),
-	SH_PFC_PIN_GROUP(audio_clkout_b),
-	SH_PFC_PIN_GROUP(audio_clkout_c),
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii),
-	SH_PFC_PIN_GROUP(avb_gmii),
-	SH_PFC_PIN_GROUP(avb_avtp_capture),
-	SH_PFC_PIN_GROUP(avb_avtp_match),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
-	SH_PFC_PIN_GROUP(avb_avtp_match_b),
-	SH_PFC_PIN_GROUP(du0_rgb666),
-	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_clk0_out),
-	SH_PFC_PIN_GROUP(du0_clk1_out),
-	SH_PFC_PIN_GROUP(du0_clk_in),
-	SH_PFC_PIN_GROUP(du0_sync),
-	SH_PFC_PIN_GROUP(du0_oddf),
-	SH_PFC_PIN_GROUP(du0_cde),
-	SH_PFC_PIN_GROUP(du0_disp),
-	SH_PFC_PIN_GROUP(du1_rgb666),
-	SH_PFC_PIN_GROUP(du1_rgb888),
-	SH_PFC_PIN_GROUP(du1_clk0_out),
-	SH_PFC_PIN_GROUP(du1_clk1_out),
-	SH_PFC_PIN_GROUP(du1_clk_in),
-	SH_PFC_PIN_GROUP(du1_sync),
-	SH_PFC_PIN_GROUP(du1_oddf),
-	SH_PFC_PIN_GROUP(du1_cde),
-	SH_PFC_PIN_GROUP(du1_disp),
-	SH_PFC_PIN_GROUP(eth_link),
-	SH_PFC_PIN_GROUP(eth_magic),
-	SH_PFC_PIN_GROUP(eth_mdio),
-	SH_PFC_PIN_GROUP(eth_rmii),
-	SH_PFC_PIN_GROUP(eth_link_b),
-	SH_PFC_PIN_GROUP(eth_magic_b),
-	SH_PFC_PIN_GROUP(eth_mdio_b),
-	SH_PFC_PIN_GROUP(eth_rmii_b),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_clk_b),
-	SH_PFC_PIN_GROUP(hscif1_data),
-	SH_PFC_PIN_GROUP(hscif1_clk),
-	SH_PFC_PIN_GROUP(hscif1_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif2_data),
-	SH_PFC_PIN_GROUP(hscif2_clk),
-	SH_PFC_PIN_GROUP(hscif2_ctrl),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c0_b),
-	SH_PFC_PIN_GROUP(i2c0_c),
-	SH_PFC_PIN_GROUP(i2c0_d),
-	SH_PFC_PIN_GROUP(i2c0_e),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c1_c),
-	SH_PFC_PIN_GROUP(i2c1_d),
-	SH_PFC_PIN_GROUP(i2c1_e),
-	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c2_c),
-	SH_PFC_PIN_GROUP(i2c2_d),
-	SH_PFC_PIN_GROUP(i2c2_e),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(i2c3_c),
-	SH_PFC_PIN_GROUP(i2c3_d),
-	SH_PFC_PIN_GROUP(i2c3_e),
-	SH_PFC_PIN_GROUP(i2c4),
-	SH_PFC_PIN_GROUP(i2c4_b),
-	SH_PFC_PIN_GROUP(i2c4_c),
-	SH_PFC_PIN_GROUP(i2c4_d),
-	SH_PFC_PIN_GROUP(i2c4_e),
-	SH_PFC_PIN_GROUP(intc_irq0),
-	SH_PFC_PIN_GROUP(intc_irq1),
-	SH_PFC_PIN_GROUP(intc_irq2),
-	SH_PFC_PIN_GROUP(intc_irq3),
-	SH_PFC_PIN_GROUP(intc_irq4),
-	SH_PFC_PIN_GROUP(intc_irq5),
-	SH_PFC_PIN_GROUP(intc_irq6),
-	SH_PFC_PIN_GROUP(intc_irq7),
-	SH_PFC_PIN_GROUP(intc_irq8),
-	SH_PFC_PIN_GROUP(intc_irq9),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_rx),
-	SH_PFC_PIN_GROUP(msiof0_tx),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_rx),
-	SH_PFC_PIN_GROUP(msiof1_tx),
-	SH_PFC_PIN_GROUP(msiof1_clk_b),
-	SH_PFC_PIN_GROUP(msiof1_sync_b),
-	SH_PFC_PIN_GROUP(msiof1_ss1_b),
-	SH_PFC_PIN_GROUP(msiof1_ss2_b),
-	SH_PFC_PIN_GROUP(msiof1_rx_b),
-	SH_PFC_PIN_GROUP(msiof1_tx_b),
-	SH_PFC_PIN_GROUP(msiof2_clk),
-	SH_PFC_PIN_GROUP(msiof2_sync),
-	SH_PFC_PIN_GROUP(msiof2_ss1),
-	SH_PFC_PIN_GROUP(msiof2_ss2),
-	SH_PFC_PIN_GROUP(msiof2_rx),
-	SH_PFC_PIN_GROUP(msiof2_tx),
-	SH_PFC_PIN_GROUP(msiof2_clk_b),
-	SH_PFC_PIN_GROUP(msiof2_sync_b),
-	SH_PFC_PIN_GROUP(msiof2_ss1_b),
-	SH_PFC_PIN_GROUP(msiof2_ss2_b),
-	SH_PFC_PIN_GROUP(msiof2_rx_b),
-	SH_PFC_PIN_GROUP(msiof2_tx_b),
-	SH_PFC_PIN_GROUP(qspi_ctrl),
-	SH_PFC_PIN_GROUP(qspi_data2),
-	SH_PFC_PIN_GROUP(qspi_data4),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif0_data_c),
-	SH_PFC_PIN_GROUP(scif0_data_d),
-	SH_PFC_PIN_GROUP(scif1_data),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_clk_b),
-	SH_PFC_PIN_GROUP(scif1_data_c),
-	SH_PFC_PIN_GROUP(scif1_clk_c),
-	SH_PFC_PIN_GROUP(scif2_data),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif2_clk_b),
-	SH_PFC_PIN_GROUP(scif2_data_c),
-	SH_PFC_PIN_GROUP(scif2_clk_c),
-	SH_PFC_PIN_GROUP(scif3_data),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif3_clk_b),
-	SH_PFC_PIN_GROUP(scif4_data),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif4_data_d),
-	SH_PFC_PIN_GROUP(scif4_data_e),
-	SH_PFC_PIN_GROUP(scif5_data),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(scif5_data_c),
-	SH_PFC_PIN_GROUP(scif5_data_d),
-	SH_PFC_PIN_GROUP(scifa0_data),
-	SH_PFC_PIN_GROUP(scifa0_data_b),
-	SH_PFC_PIN_GROUP(scifa0_data_c),
-	SH_PFC_PIN_GROUP(scifa0_data_d),
-	SH_PFC_PIN_GROUP(scifa1_data),
-	SH_PFC_PIN_GROUP(scifa1_clk),
-	SH_PFC_PIN_GROUP(scifa1_data_b),
-	SH_PFC_PIN_GROUP(scifa1_clk_b),
-	SH_PFC_PIN_GROUP(scifa1_data_c),
-	SH_PFC_PIN_GROUP(scifa1_clk_c),
-	SH_PFC_PIN_GROUP(scifa2_data),
-	SH_PFC_PIN_GROUP(scifa2_clk),
-	SH_PFC_PIN_GROUP(scifa2_data_b),
-	SH_PFC_PIN_GROUP(scifa2_clk_b),
-	SH_PFC_PIN_GROUP(scifa3_data),
-	SH_PFC_PIN_GROUP(scifa3_clk),
-	SH_PFC_PIN_GROUP(scifa3_data_b),
-	SH_PFC_PIN_GROUP(scifa3_clk_b),
-	SH_PFC_PIN_GROUP(scifa4_data),
-	SH_PFC_PIN_GROUP(scifa4_data_b),
-	SH_PFC_PIN_GROUP(scifa4_data_c),
-	SH_PFC_PIN_GROUP(scifa4_data_d),
-	SH_PFC_PIN_GROUP(scifa5_data),
-	SH_PFC_PIN_GROUP(scifa5_data_b),
-	SH_PFC_PIN_GROUP(scifa5_data_c),
-	SH_PFC_PIN_GROUP(scifa5_data_d),
-	SH_PFC_PIN_GROUP(scifb0_data),
-	SH_PFC_PIN_GROUP(scifb0_clk),
-	SH_PFC_PIN_GROUP(scifb0_ctrl),
-	SH_PFC_PIN_GROUP(scifb1_data),
-	SH_PFC_PIN_GROUP(scifb1_clk),
-	SH_PFC_PIN_GROUP(scifb2_data),
-	SH_PFC_PIN_GROUP(scifb2_clk),
-	SH_PFC_PIN_GROUP(scifb2_ctrl),
-	SH_PFC_PIN_GROUP(scif_clk),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd),
-	SH_PFC_PIN_GROUP(sdhi2_wp),
-	SH_PFC_PIN_GROUP(ssi0_data),
-	SH_PFC_PIN_GROUP(ssi0129_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data),
-	SH_PFC_PIN_GROUP(ssi1_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data_b),
-	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi2_data),
-	SH_PFC_PIN_GROUP(ssi2_ctrl),
-	SH_PFC_PIN_GROUP(ssi2_data_b),
-	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi34_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data),
-	SH_PFC_PIN_GROUP(ssi4_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data_b),
-	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi5_data),
-	SH_PFC_PIN_GROUP(ssi5_ctrl),
-	SH_PFC_PIN_GROUP(ssi5_data_b),
-	SH_PFC_PIN_GROUP(ssi5_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi6_data),
-	SH_PFC_PIN_GROUP(ssi6_ctrl),
-	SH_PFC_PIN_GROUP(ssi6_data_b),
-	SH_PFC_PIN_GROUP(ssi6_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi7_data),
-	SH_PFC_PIN_GROUP(ssi78_ctrl),
-	SH_PFC_PIN_GROUP(ssi7_data_b),
-	SH_PFC_PIN_GROUP(ssi78_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi8_data),
-	SH_PFC_PIN_GROUP(ssi8_data_b),
-	SH_PFC_PIN_GROUP(ssi9_data),
-	SH_PFC_PIN_GROUP(ssi9_ctrl),
-	SH_PFC_PIN_GROUP(ssi9_data_b),
-	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb1),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
+static const struct {
+	struct sh_pfc_pin_group common[264];
+	struct sh_pfc_pin_group r8a7794[4];
+} pinmux_groups = {
+	.common = {
+		SH_PFC_PIN_GROUP(audio_clka),
+		SH_PFC_PIN_GROUP(audio_clka_b),
+		SH_PFC_PIN_GROUP(audio_clka_c),
+		SH_PFC_PIN_GROUP(audio_clka_d),
+		SH_PFC_PIN_GROUP(audio_clkb),
+		SH_PFC_PIN_GROUP(audio_clkb_b),
+		SH_PFC_PIN_GROUP(audio_clkb_c),
+		SH_PFC_PIN_GROUP(audio_clkc),
+		SH_PFC_PIN_GROUP(audio_clkc_b),
+		SH_PFC_PIN_GROUP(audio_clkc_c),
+		SH_PFC_PIN_GROUP(audio_clkout),
+		SH_PFC_PIN_GROUP(audio_clkout_b),
+		SH_PFC_PIN_GROUP(audio_clkout_c),
+		SH_PFC_PIN_GROUP(avb_link),
+		SH_PFC_PIN_GROUP(avb_magic),
+		SH_PFC_PIN_GROUP(avb_phy_int),
+		SH_PFC_PIN_GROUP(avb_mdio),
+		SH_PFC_PIN_GROUP(avb_mii),
+		SH_PFC_PIN_GROUP(avb_gmii),
+		SH_PFC_PIN_GROUP(du0_rgb666),
+		SH_PFC_PIN_GROUP(du0_rgb888),
+		SH_PFC_PIN_GROUP(du0_clk0_out),
+		SH_PFC_PIN_GROUP(du0_clk1_out),
+		SH_PFC_PIN_GROUP(du0_clk_in),
+		SH_PFC_PIN_GROUP(du0_sync),
+		SH_PFC_PIN_GROUP(du0_oddf),
+		SH_PFC_PIN_GROUP(du0_cde),
+		SH_PFC_PIN_GROUP(du0_disp),
+		SH_PFC_PIN_GROUP(du1_rgb666),
+		SH_PFC_PIN_GROUP(du1_rgb888),
+		SH_PFC_PIN_GROUP(du1_clk0_out),
+		SH_PFC_PIN_GROUP(du1_clk1_out),
+		SH_PFC_PIN_GROUP(du1_clk_in),
+		SH_PFC_PIN_GROUP(du1_sync),
+		SH_PFC_PIN_GROUP(du1_oddf),
+		SH_PFC_PIN_GROUP(du1_cde),
+		SH_PFC_PIN_GROUP(du1_disp),
+		SH_PFC_PIN_GROUP(eth_link),
+		SH_PFC_PIN_GROUP(eth_magic),
+		SH_PFC_PIN_GROUP(eth_mdio),
+		SH_PFC_PIN_GROUP(eth_rmii),
+		SH_PFC_PIN_GROUP(eth_link_b),
+		SH_PFC_PIN_GROUP(eth_magic_b),
+		SH_PFC_PIN_GROUP(eth_mdio_b),
+		SH_PFC_PIN_GROUP(eth_rmii_b),
+		SH_PFC_PIN_GROUP(hscif0_data),
+		SH_PFC_PIN_GROUP(hscif0_clk),
+		SH_PFC_PIN_GROUP(hscif0_ctrl),
+		SH_PFC_PIN_GROUP(hscif0_data_b),
+		SH_PFC_PIN_GROUP(hscif0_clk_b),
+		SH_PFC_PIN_GROUP(hscif1_data),
+		SH_PFC_PIN_GROUP(hscif1_clk),
+		SH_PFC_PIN_GROUP(hscif1_ctrl),
+		SH_PFC_PIN_GROUP(hscif1_data_b),
+		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+		SH_PFC_PIN_GROUP(hscif2_data),
+		SH_PFC_PIN_GROUP(hscif2_clk),
+		SH_PFC_PIN_GROUP(hscif2_ctrl),
+		SH_PFC_PIN_GROUP(i2c0),
+		SH_PFC_PIN_GROUP(i2c0_b),
+		SH_PFC_PIN_GROUP(i2c0_c),
+		SH_PFC_PIN_GROUP(i2c0_d),
+		SH_PFC_PIN_GROUP(i2c0_e),
+		SH_PFC_PIN_GROUP(i2c1),
+		SH_PFC_PIN_GROUP(i2c1_b),
+		SH_PFC_PIN_GROUP(i2c1_c),
+		SH_PFC_PIN_GROUP(i2c1_d),
+		SH_PFC_PIN_GROUP(i2c1_e),
+		SH_PFC_PIN_GROUP(i2c2),
+		SH_PFC_PIN_GROUP(i2c2_b),
+		SH_PFC_PIN_GROUP(i2c2_c),
+		SH_PFC_PIN_GROUP(i2c2_d),
+		SH_PFC_PIN_GROUP(i2c2_e),
+		SH_PFC_PIN_GROUP(i2c3),
+		SH_PFC_PIN_GROUP(i2c3_b),
+		SH_PFC_PIN_GROUP(i2c3_c),
+		SH_PFC_PIN_GROUP(i2c3_d),
+		SH_PFC_PIN_GROUP(i2c3_e),
+		SH_PFC_PIN_GROUP(i2c4),
+		SH_PFC_PIN_GROUP(i2c4_b),
+		SH_PFC_PIN_GROUP(i2c4_c),
+		SH_PFC_PIN_GROUP(i2c4_d),
+		SH_PFC_PIN_GROUP(i2c4_e),
+		SH_PFC_PIN_GROUP(intc_irq0),
+		SH_PFC_PIN_GROUP(intc_irq1),
+		SH_PFC_PIN_GROUP(intc_irq2),
+		SH_PFC_PIN_GROUP(intc_irq3),
+		SH_PFC_PIN_GROUP(intc_irq4),
+		SH_PFC_PIN_GROUP(intc_irq5),
+		SH_PFC_PIN_GROUP(intc_irq6),
+		SH_PFC_PIN_GROUP(intc_irq7),
+		SH_PFC_PIN_GROUP(intc_irq8),
+		SH_PFC_PIN_GROUP(intc_irq9),
+		SH_PFC_PIN_GROUP(mmc_data1),
+		SH_PFC_PIN_GROUP(mmc_data4),
+		SH_PFC_PIN_GROUP(mmc_data8),
+		SH_PFC_PIN_GROUP(mmc_ctrl),
+		SH_PFC_PIN_GROUP(msiof0_clk),
+		SH_PFC_PIN_GROUP(msiof0_sync),
+		SH_PFC_PIN_GROUP(msiof0_ss1),
+		SH_PFC_PIN_GROUP(msiof0_ss2),
+		SH_PFC_PIN_GROUP(msiof0_rx),
+		SH_PFC_PIN_GROUP(msiof0_tx),
+		SH_PFC_PIN_GROUP(msiof1_clk),
+		SH_PFC_PIN_GROUP(msiof1_sync),
+		SH_PFC_PIN_GROUP(msiof1_ss1),
+		SH_PFC_PIN_GROUP(msiof1_ss2),
+		SH_PFC_PIN_GROUP(msiof1_rx),
+		SH_PFC_PIN_GROUP(msiof1_tx),
+		SH_PFC_PIN_GROUP(msiof1_clk_b),
+		SH_PFC_PIN_GROUP(msiof1_sync_b),
+		SH_PFC_PIN_GROUP(msiof1_ss1_b),
+		SH_PFC_PIN_GROUP(msiof1_ss2_b),
+		SH_PFC_PIN_GROUP(msiof1_rx_b),
+		SH_PFC_PIN_GROUP(msiof1_tx_b),
+		SH_PFC_PIN_GROUP(msiof2_clk),
+		SH_PFC_PIN_GROUP(msiof2_sync),
+		SH_PFC_PIN_GROUP(msiof2_ss1),
+		SH_PFC_PIN_GROUP(msiof2_ss2),
+		SH_PFC_PIN_GROUP(msiof2_rx),
+		SH_PFC_PIN_GROUP(msiof2_tx),
+		SH_PFC_PIN_GROUP(msiof2_clk_b),
+		SH_PFC_PIN_GROUP(msiof2_sync_b),
+		SH_PFC_PIN_GROUP(msiof2_ss1_b),
+		SH_PFC_PIN_GROUP(msiof2_ss2_b),
+		SH_PFC_PIN_GROUP(msiof2_rx_b),
+		SH_PFC_PIN_GROUP(msiof2_tx_b),
+		SH_PFC_PIN_GROUP(qspi_ctrl),
+		SH_PFC_PIN_GROUP(qspi_data2),
+		SH_PFC_PIN_GROUP(qspi_data4),
+		SH_PFC_PIN_GROUP(scif0_data),
+		SH_PFC_PIN_GROUP(scif0_data_b),
+		SH_PFC_PIN_GROUP(scif0_data_c),
+		SH_PFC_PIN_GROUP(scif0_data_d),
+		SH_PFC_PIN_GROUP(scif1_data),
+		SH_PFC_PIN_GROUP(scif1_clk),
+		SH_PFC_PIN_GROUP(scif1_data_b),
+		SH_PFC_PIN_GROUP(scif1_clk_b),
+		SH_PFC_PIN_GROUP(scif1_data_c),
+		SH_PFC_PIN_GROUP(scif1_clk_c),
+		SH_PFC_PIN_GROUP(scif2_data),
+		SH_PFC_PIN_GROUP(scif2_clk),
+		SH_PFC_PIN_GROUP(scif2_data_b),
+		SH_PFC_PIN_GROUP(scif2_clk_b),
+		SH_PFC_PIN_GROUP(scif2_data_c),
+		SH_PFC_PIN_GROUP(scif2_clk_c),
+		SH_PFC_PIN_GROUP(scif3_data),
+		SH_PFC_PIN_GROUP(scif3_clk),
+		SH_PFC_PIN_GROUP(scif3_data_b),
+		SH_PFC_PIN_GROUP(scif3_clk_b),
+		SH_PFC_PIN_GROUP(scif4_data),
+		SH_PFC_PIN_GROUP(scif4_data_b),
+		SH_PFC_PIN_GROUP(scif4_data_c),
+		SH_PFC_PIN_GROUP(scif4_data_d),
+		SH_PFC_PIN_GROUP(scif4_data_e),
+		SH_PFC_PIN_GROUP(scif5_data),
+		SH_PFC_PIN_GROUP(scif5_data_b),
+		SH_PFC_PIN_GROUP(scif5_data_c),
+		SH_PFC_PIN_GROUP(scif5_data_d),
+		SH_PFC_PIN_GROUP(scifa0_data),
+		SH_PFC_PIN_GROUP(scifa0_data_b),
+		SH_PFC_PIN_GROUP(scifa0_data_c),
+		SH_PFC_PIN_GROUP(scifa0_data_d),
+		SH_PFC_PIN_GROUP(scifa1_data),
+		SH_PFC_PIN_GROUP(scifa1_clk),
+		SH_PFC_PIN_GROUP(scifa1_data_b),
+		SH_PFC_PIN_GROUP(scifa1_clk_b),
+		SH_PFC_PIN_GROUP(scifa1_data_c),
+		SH_PFC_PIN_GROUP(scifa1_clk_c),
+		SH_PFC_PIN_GROUP(scifa2_data),
+		SH_PFC_PIN_GROUP(scifa2_clk),
+		SH_PFC_PIN_GROUP(scifa2_data_b),
+		SH_PFC_PIN_GROUP(scifa2_clk_b),
+		SH_PFC_PIN_GROUP(scifa3_data),
+		SH_PFC_PIN_GROUP(scifa3_clk),
+		SH_PFC_PIN_GROUP(scifa3_data_b),
+		SH_PFC_PIN_GROUP(scifa3_clk_b),
+		SH_PFC_PIN_GROUP(scifa4_data),
+		SH_PFC_PIN_GROUP(scifa4_data_b),
+		SH_PFC_PIN_GROUP(scifa4_data_c),
+		SH_PFC_PIN_GROUP(scifa4_data_d),
+		SH_PFC_PIN_GROUP(scifa5_data),
+		SH_PFC_PIN_GROUP(scifa5_data_b),
+		SH_PFC_PIN_GROUP(scifa5_data_c),
+		SH_PFC_PIN_GROUP(scifa5_data_d),
+		SH_PFC_PIN_GROUP(scifb0_data),
+		SH_PFC_PIN_GROUP(scifb0_clk),
+		SH_PFC_PIN_GROUP(scifb0_ctrl),
+		SH_PFC_PIN_GROUP(scifb1_data),
+		SH_PFC_PIN_GROUP(scifb1_clk),
+		SH_PFC_PIN_GROUP(scifb2_data),
+		SH_PFC_PIN_GROUP(scifb2_clk),
+		SH_PFC_PIN_GROUP(scifb2_ctrl),
+		SH_PFC_PIN_GROUP(scif_clk),
+		SH_PFC_PIN_GROUP(scif_clk_b),
+		SH_PFC_PIN_GROUP(sdhi0_data1),
+		SH_PFC_PIN_GROUP(sdhi0_data4),
+		SH_PFC_PIN_GROUP(sdhi0_ctrl),
+		SH_PFC_PIN_GROUP(sdhi0_cd),
+		SH_PFC_PIN_GROUP(sdhi0_wp),
+		SH_PFC_PIN_GROUP(sdhi1_data1),
+		SH_PFC_PIN_GROUP(sdhi1_data4),
+		SH_PFC_PIN_GROUP(sdhi1_ctrl),
+		SH_PFC_PIN_GROUP(sdhi1_cd),
+		SH_PFC_PIN_GROUP(sdhi1_wp),
+		SH_PFC_PIN_GROUP(sdhi2_data1),
+		SH_PFC_PIN_GROUP(sdhi2_data4),
+		SH_PFC_PIN_GROUP(sdhi2_ctrl),
+		SH_PFC_PIN_GROUP(sdhi2_cd),
+		SH_PFC_PIN_GROUP(sdhi2_wp),
+		SH_PFC_PIN_GROUP(ssi0_data),
+		SH_PFC_PIN_GROUP(ssi0129_ctrl),
+		SH_PFC_PIN_GROUP(ssi1_data),
+		SH_PFC_PIN_GROUP(ssi1_ctrl),
+		SH_PFC_PIN_GROUP(ssi1_data_b),
+		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+		SH_PFC_PIN_GROUP(ssi2_data),
+		SH_PFC_PIN_GROUP(ssi2_ctrl),
+		SH_PFC_PIN_GROUP(ssi2_data_b),
+		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
+		SH_PFC_PIN_GROUP(ssi3_data),
+		SH_PFC_PIN_GROUP(ssi34_ctrl),
+		SH_PFC_PIN_GROUP(ssi4_data),
+		SH_PFC_PIN_GROUP(ssi4_ctrl),
+		SH_PFC_PIN_GROUP(ssi4_data_b),
+		SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+		SH_PFC_PIN_GROUP(ssi5_data),
+		SH_PFC_PIN_GROUP(ssi5_ctrl),
+		SH_PFC_PIN_GROUP(ssi5_data_b),
+		SH_PFC_PIN_GROUP(ssi5_ctrl_b),
+		SH_PFC_PIN_GROUP(ssi6_data),
+		SH_PFC_PIN_GROUP(ssi6_ctrl),
+		SH_PFC_PIN_GROUP(ssi6_data_b),
+		SH_PFC_PIN_GROUP(ssi6_ctrl_b),
+		SH_PFC_PIN_GROUP(ssi7_data),
+		SH_PFC_PIN_GROUP(ssi78_ctrl),
+		SH_PFC_PIN_GROUP(ssi7_data_b),
+		SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+		SH_PFC_PIN_GROUP(ssi8_data),
+		SH_PFC_PIN_GROUP(ssi8_data_b),
+		SH_PFC_PIN_GROUP(ssi9_data),
+		SH_PFC_PIN_GROUP(ssi9_ctrl),
+		SH_PFC_PIN_GROUP(ssi9_data_b),
+		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+		SH_PFC_PIN_GROUP(usb0),
+		SH_PFC_PIN_GROUP(usb1),
+		VIN_DATA_PIN_GROUP(vin0_data, 24),
+		VIN_DATA_PIN_GROUP(vin0_data, 20),
+		SH_PFC_PIN_GROUP(vin0_data18),
+		VIN_DATA_PIN_GROUP(vin0_data, 16),
+		VIN_DATA_PIN_GROUP(vin0_data, 12),
+		VIN_DATA_PIN_GROUP(vin0_data, 10),
+		VIN_DATA_PIN_GROUP(vin0_data, 8),
+		SH_PFC_PIN_GROUP(vin0_sync),
+		SH_PFC_PIN_GROUP(vin0_field),
+		SH_PFC_PIN_GROUP(vin0_clkenb),
+		SH_PFC_PIN_GROUP(vin0_clk),
+		VIN_DATA_PIN_GROUP(vin1_data, 12),
+		VIN_DATA_PIN_GROUP(vin1_data, 10),
+		VIN_DATA_PIN_GROUP(vin1_data, 8),
+		SH_PFC_PIN_GROUP(vin1_sync),
+		SH_PFC_PIN_GROUP(vin1_field),
+		SH_PFC_PIN_GROUP(vin1_clkenb),
+		SH_PFC_PIN_GROUP(vin1_clk),
+	},
+	.r8a7794 = {
+		SH_PFC_PIN_GROUP(avb_avtp_capture),
+		SH_PFC_PIN_GROUP(avb_avtp_match),
+		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+		SH_PFC_PIN_GROUP(avb_avtp_match_b),
+	}
 };
 
 static const char * const audio_clk_groups[] = {
@@ -3809,6 +4055,9 @@  static const char * const avb_groups[] =
 	"avb_mdio",
 	"avb_mii",
 	"avb_gmii",
+};
+
+static const char * const avb_avtp_groups[] = {
 	"avb_avtp_capture",
 	"avb_avtp_match",
 	"avb_avtp_capture_b",
@@ -4183,50 +4432,58 @@  static const char * const vin1_groups[]
 	"vin1_clk",
 };
 
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(du0),
-	SH_PFC_FUNCTION(du1),
-	SH_PFC_FUNCTION(eth),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hscif2),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c4),
-	SH_PFC_FUNCTION(intc),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(qspi),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scifa0),
-	SH_PFC_FUNCTION(scifa1),
-	SH_PFC_FUNCTION(scifa2),
-	SH_PFC_FUNCTION(scifa3),
-	SH_PFC_FUNCTION(scifa4),
-	SH_PFC_FUNCTION(scifa5),
-	SH_PFC_FUNCTION(scifb0),
-	SH_PFC_FUNCTION(scifb1),
-	SH_PFC_FUNCTION(scifb2),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
+static const struct {
+	struct sh_pfc_function common[43];
+	struct sh_pfc_function r8a7794[1];
+} pinmux_functions = {
+	.common = {
+		SH_PFC_FUNCTION(audio_clk),
+		SH_PFC_FUNCTION(avb),
+		SH_PFC_FUNCTION(du0),
+		SH_PFC_FUNCTION(du1),
+		SH_PFC_FUNCTION(eth),
+		SH_PFC_FUNCTION(hscif0),
+		SH_PFC_FUNCTION(hscif1),
+		SH_PFC_FUNCTION(hscif2),
+		SH_PFC_FUNCTION(i2c0),
+		SH_PFC_FUNCTION(i2c1),
+		SH_PFC_FUNCTION(i2c2),
+		SH_PFC_FUNCTION(i2c3),
+		SH_PFC_FUNCTION(i2c4),
+		SH_PFC_FUNCTION(intc),
+		SH_PFC_FUNCTION(mmc),
+		SH_PFC_FUNCTION(msiof0),
+		SH_PFC_FUNCTION(msiof1),
+		SH_PFC_FUNCTION(msiof2),
+		SH_PFC_FUNCTION(qspi),
+		SH_PFC_FUNCTION(scif0),
+		SH_PFC_FUNCTION(scif1),
+		SH_PFC_FUNCTION(scif2),
+		SH_PFC_FUNCTION(scif3),
+		SH_PFC_FUNCTION(scif4),
+		SH_PFC_FUNCTION(scif5),
+		SH_PFC_FUNCTION(scifa0),
+		SH_PFC_FUNCTION(scifa1),
+		SH_PFC_FUNCTION(scifa2),
+		SH_PFC_FUNCTION(scifa3),
+		SH_PFC_FUNCTION(scifa4),
+		SH_PFC_FUNCTION(scifa5),
+		SH_PFC_FUNCTION(scifb0),
+		SH_PFC_FUNCTION(scifb1),
+		SH_PFC_FUNCTION(scifb2),
+		SH_PFC_FUNCTION(scif_clk),
+		SH_PFC_FUNCTION(sdhi0),
+		SH_PFC_FUNCTION(sdhi1),
+		SH_PFC_FUNCTION(sdhi2),
+		SH_PFC_FUNCTION(ssi),
+		SH_PFC_FUNCTION(usb0),
+		SH_PFC_FUNCTION(usb1),
+		SH_PFC_FUNCTION(vin0),
+		SH_PFC_FUNCTION(vin1),
+	},
+	.r8a7794 = {
+		SH_PFC_FUNCTION(avb_avtp),
+	}
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -5012,24 +5269,24 @@  static const struct pinmux_cfg_reg pinmu
 			     2, 1) {
 		/* SEL_ADG [2] */
 		FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
-		/* SEL_ADI [1] */
+		/* SEL_ADI [1] (R8A7794 only) */
 		FN_SEL_ADI_0, FN_SEL_ADI_1,
 		/* SEL_CAN [2] */
 		FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
-		/* SEL_DARC [3] */
+		/* SEL_DARC [3] (R8A7794 only) */
 		FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
 		FN_SEL_DARC_4, 0, 0, 0,
-		/* SEL_DR0 [1] */
+		/* SEL_DR0 [1] (R8A7794 only) */
 		FN_SEL_DR0_0, FN_SEL_DR0_1,
-		/* SEL_DR1 [1] */
+		/* SEL_DR1 [1]  (R8A7794 only)*/
 		FN_SEL_DR1_0, FN_SEL_DR1_1,
-		/* SEL_DR2 [1] */
+		/* SEL_DR2 [1] (R8A7794 only) */
 		FN_SEL_DR2_0, FN_SEL_DR2_1,
-		/* SEL_DR3 [1] */
+		/* SEL_DR3 [1] (R8A7794 only) */
 		FN_SEL_DR3_0, FN_SEL_DR3_1,
 		/* SEL_ETH [1] */
 		FN_SEL_ETH_0, FN_SEL_ETH_1,
-		/* SLE_FSN [1] */
+		/* SEL_FSN [1] (R8A7794 only) */
 		FN_SEL_FSN_0, FN_SEL_FSN_1,
 		/* SEL_IC200 [3] */
 		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
@@ -5054,7 +5311,7 @@  static const struct pinmux_cfg_reg pinmu
 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
 			     2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
 			     2, 2, 2, 1, 1, 2) {
-		/* SEL_IEB [2] */
+		/* SEL_IEB [2] (R8A7794 only) */
 		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
 		/* SEL_IIC0 [2] */
 		FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
@@ -5066,9 +5323,9 @@  static const struct pinmux_cfg_reg pinmu
 		FN_SEL_MSI2_0, FN_SEL_MSI2_1,
 		/* SEL_RAD [1] */
 		FN_SEL_RAD_0, FN_SEL_RAD_1,
-		/* SEL_RCN [1] */
+		/* SEL_RCN [1] (R8A7794 only) */
 		FN_SEL_RCN_0, FN_SEL_RCN_1,
-		/* SEL_RSP [1] */
+		/* SEL_RSP [1] (R8A7794 only) */
 		FN_SEL_RSP_0, FN_SEL_RSP_1,
 		/* SEL_SCIFA0 [2] */
 		FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
@@ -5085,11 +5342,11 @@  static const struct pinmux_cfg_reg pinmu
 		/* SEL_SCIFA5 [2] */
 		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 		FN_SEL_SCIFA5_3,
-		/* SEL_SPDM [1] */
+		/* SEL_SPDM [1] (R8A7794 only) */
 		FN_SEL_SPDM_0, FN_SEL_SPDM_1,
 		/* SEL_TMU [1] */
 		FN_SEL_TMU_0, FN_SEL_TMU_1,
-		/* SEL_TSIF0 [2] */
+		/* SEL_TSIF0 [2] (R8A7794 only) */
 		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 		/* SEL_CAN0 [2] */
 		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
@@ -5099,7 +5356,7 @@  static const struct pinmux_cfg_reg pinmu
 		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 		/* SEL_HSCIF1 [1] */
 		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-		/* SEL_RDS [2] */
+		/* SEL_RDS [2] (R8A7794 only) */
 		FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
 	},
 	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
@@ -5185,6 +5442,28 @@  static const struct sh_pfc_soc_operation
 	.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+const struct sh_pfc_soc_info r8a7745_pinmux_info = {
+	.name = "r8a77450_pfc",
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups.common,
+	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
+	.functions = pinmux_functions.common,
+	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
+
+	.cfg_regs = pinmux_config_regs,
+
+	.pinmux_data = pinmux_data,
+	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7794
 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
 	.name = "r8a77940_pfc",
 	.ops = &r8a7794_pinmux_ops,
@@ -5194,13 +5473,16 @@  const struct sh_pfc_soc_info r8a7794_pin
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
+	.groups = pinmux_groups.common,
+	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+		     ARRAY_SIZE(pinmux_groups.r8a7794),
+	.functions = pinmux_functions.common,
+	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+			ARRAY_SIZE(pinmux_functions.r8a7794),
 
 	.cfg_regs = pinmux_config_regs,
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
 };
+#endif
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -260,6 +260,7 @@  extern const struct sh_pfc_soc_info emev
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;