@@ -49,6 +49,29 @@ config ARCH_LS1046A
select BOARD_EARLY_INIT_F
select SYS_FSL_HAS_CCI400
+config ARCH_LS1088A
+ bool
+ select ARMV8_SET_SMPEN
+ select FSL_LSCH3
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_CCI400
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
+ select FSL_TZASC_1
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008850
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
@@ -79,6 +102,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
+ select SYS_FSL_HAS_CCN504
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -97,7 +121,7 @@ config FSL_LSCH3
config FSL_MC_ENET
bool "Management Complex network"
- depends on ARCH_LS2080A
+ depends on ARCH_LS2080A || ARCH_LS1088A
default y
select RESV_RAM
help
@@ -113,6 +137,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
+ default "fsl,ls1080a-pcie" if ARCH_LS1088A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
@@ -173,6 +198,7 @@ config MAX_CPUS
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
+ default 8 if ARCH_LS1088A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
@@ -195,13 +221,11 @@ config QSPI_AHB_INIT
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+ depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
- default 8 if ARCH_LS2080A
+ default 8 if ARCH_LS2080A || ARCH_LS1088A
-config SYS_FSL_HAS_CCI400
- bool
config SYS_FSL_HAS_DP_DDR
bool
@@ -244,6 +268,7 @@ config SYS_FSL_PCLK_DIV
int "Platform clock divider"
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
+ default 1 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive Platform clock from
@@ -313,6 +338,12 @@ config RESV_RAM
config SYS_FSL_ERRATUM_A009203
bool
+config SYS_FSL_HAS_CCI400
+ bool
+
+config SYS_FSL_HAS_CCN504
+ bool
+
config SYS_FSL_ERRATUM_A008336
bool
@@ -337,7 +368,8 @@ config SYS_FSL_ERRATUM_A009929
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
- default 0x20000000
+ default 0x20000000 if ARCH_LS2080A
+ default 0x70000000 if ARCH_LS1088A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
@@ -38,3 +38,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
endif
+
+ifneq ($(CONFIG_ARCH_LS1088A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+endif
@@ -14,6 +14,7 @@
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
+#include <fsl_immap.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
@@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
return;
}
+__weak int serdes_get_number(int serdes, int cfg)
+{
+ return cfg;
+}
+
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
@@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
printf("invalid SerDes%d\n", sd);
break;
}
+
+ cfg = serdes_get_number(sd, cfg);
+
/* Is serdes enabled at all? */
if (cfg == 0)
return -ENODEV;
@@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
+
+ cfg = serdes_get_number(sd, cfg);
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
@@ -73,7 +73,7 @@ ENDPROC(smp_kick_all_cpus)
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_LS2080A
@@ -328,7 +328,9 @@ get_svr:
ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1]
ret
+#endif
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
@@ -406,7 +408,7 @@ ENTRY(__asm_flush_l3_dcache)
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
new file mode 100644
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+
+struct serdes_config {
+ u8 ip_protocol;
+ u8 lanes[SRDS_MAX_LANES];
+ u8 rcw_lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },
+ {0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
+ {0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
+ {0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
+ {0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
+ {0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
+ {0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
+ {0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
+ {0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
+ {0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
+ {0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },
+ {0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } },
+ {0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
+ {0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
+ {0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
+ {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
+ {0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } },
+ {0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } },
+ {0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } },
+ {0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } },
+ {0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+int serdes_get_number(int serdes, int cfg)
+{
+ struct serdes_config *ptr;
+ int i, j, index, lnk;
+ int is_found, max_lane = SRDS_MAX_LANES;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+
+ while (ptr->ip_protocol) {
+ is_found = 1;
+ for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
+ lnk = cfg & (0xf << 4 * i);
+ lnk = lnk >> (4 * i);
+
+ index = (serdes == FSL_SRDS_1) ? j : i;
+
+ if (ptr->rcw_lanes[index] == lnk && is_found)
+ is_found = 1;
+ else
+ is_found = 0;
+ }
+
+ if (is_found)
+ return ptr->ip_protocol;
+ ptr++;
+ }
+
+ return 0;
+}
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->ip_protocol) {
+ if (ptr->ip_protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->ip_protocol) {
+ if (ptr->ip_protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->ip_protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
@@ -24,6 +24,7 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
+#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -215,11 +216,14 @@ int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci;
+#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
+#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
@@ -227,6 +231,7 @@ int sata_init(void)
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);
+#endif
return 0;
}
new file mode 100644
@@ -0,0 +1,78 @@
+/*
+ * NXP ls1088a SOC common device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ compatible = "fsl,ls2080a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ /* DRAM space - 1, size : 2 GB DRAM */
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <1 9 0x4>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+ <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
+ <1 11 0x8>, /* Virtual PPI, active-low */
+ <1 10 0x8>; /* Hypervisor PPI, active-low */
+ };
+
+ serial0: serial@21c0500 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ serial1: serial@21c0600 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ fsl_mc: fsl-mc@80c000000 {
+ compatible = "fsl,qoriq-mc";
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ };
+
+ dspi: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 26 0x4>; /* Level high type */
+ num-cs = <6>;
+ };
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <4>;
+ };
+};
@@ -115,6 +115,67 @@
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
+#elif defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+#define CONFIG_SYS_PAGE_SIZE 0x10000
+
+#define SRDS_MAX_LANES 4
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
@@ -212,7 +273,6 @@
#define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-
#else
#error SoC not defined
#endif
@@ -21,6 +21,10 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+ CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+ CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+ CPU_TYPE_ENTRY(LS1044A, LS1048A, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
@@ -9,7 +9,7 @@
#include <config.h>
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_FSL_LSCH3
enum srds_prtcl {
/*
* Nobody will check whether the device 'NONE' has been configured,
@@ -158,6 +158,7 @@ void fsl_serdes_init(void);
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_get_number(int serdes, int cfg);
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
@@ -245,6 +245,17 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
+#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
+#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
+#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR 29
+#define FSL_CHASSIS3_SRDS2_REGSR 30
#endif
#define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400
new file mode 100644
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#ifndef __LS1088A_STREAM_ID_H
+#define __LS1088A_STREAM_ID_H
+
+/* Stream IDs on ls1088a devices are not hardwired and are
+ * programmed by sw. There are a limited number of stream IDs
+ * available, and the partitioning of them is scenario dependent.
+ * This header defines the partitioning between legacy, PCI,
+ * and DPAA2 devices.
+ *
+ * This partitiong can be customized in this file depending
+ * on the specific hardware config-- e.g. perhaps not all
+ * PEX controllers are in use.
+ *
+ * On LS1088 stream IDs are programmed in AMQ registers (32-bits) for
+ * each of the different bus masters. The relationship between
+ * the AMQ registers and stream IDs is defined in the table below:
+ * AMQ bit streamID bit
+ * ---------------------------
+ * PL[18] 9
+ * BMT[17] 8
+ * VA[16] 7
+ * [15] -
+ * ICID[14:7] -
+ * ICID[6:0] 6-0
+ * ----------------------------
+ */
+
+#define AMQ_PL_MASK (0x1 << 18) /* privilege bit */
+#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
+
+#define FSL_INVALID_STREAM_ID 0
+
+#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID 1
+#define FSL_USB2_STREAM_ID 2
+#define FSL_SDMMC_STREAM_ID 3
+#define FSL_SATA1_STREAM_ID 4
+#define FSL_DMA_STREAM_ID 5
+
+/* PCI - programmed in PEXn_LUT by OS */
+/* 4 IDs per controller */
+#define FSL_PEX_STREAM_ID_START 7
+#define FSL_PEX_STREAM_ID_END 18
+
+/* DPAA2 - set in MC DPC and alloced by MC */
+#define FSL_DPAA2_STREAM_ID_START 23
+#define FSL_DPAA2_STREAM_ID_END 63
+
+#endif
@@ -54,6 +54,10 @@ struct cpu_type {
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
+#define SVR_LS1048A 0x870320
+#define SVR_LS1084A 0x870302
+#define SVR_LS1088A 0x870300
+#define SVR_LS1044A 0x870322
#define SVR_DEV_LS2080A 0x8701
@@ -386,7 +386,7 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
void remove_unused_controllers(fsl_ddr_info_t *info)
{
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
int i;
u64 nodeid;
void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
@@ -7,3 +7,4 @@
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
obj-$(CONFIG_LS2080A) += ls2080a.o
+obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
new file mode 100644
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+u32 dpmac_to_devdisr[] = {
+ [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
+ [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
+ [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
+ [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
+ [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
+ [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
+ [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
+ [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
+ [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
+ [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
+};
+
+static int is_device_disabled(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 devdisr2 = in_le32(&gur->devdisr2);
+
+ return dpmac_to_devdisr[dpmac_id] & devdisr2;
+}
+
+void wriop_dpmac_disable(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+void wriop_dpmac_enable(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
+{
+ enum srds_prtcl;
+
+ if (is_device_disabled(dpmac_id + 1))
+ return PHY_INTERFACE_MODE_NONE;
+
+ switch (lane_prtcl) {
+ case SGMII1:
+ case SGMII2:
+ case SGMII3:
+ case SGMII7:
+ return PHY_INTERFACE_MODE_SGMII;
+ }
+
+ if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
+ return PHY_INTERFACE_MODE_QSGMII;
+
+ return PHY_INTERFACE_MODE_NONE;
+}
+
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+ switch (lane_prtcl) {
+ case QSGMII_A:
+ wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+ break;
+ case QSGMII_B:
+ wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 10, (int)lane_prtcl);
+ break;
+ }
+}