Patchwork fsldma: fix issue of slow dma

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Submitter Yang Li
Date Dec. 9, 2010, 8:14 a.m.
Message ID <1291882444-1523-1-git-send-email-leoli@freescale.com>
Download mbox | patch
Permalink /patch/74854/
State Not Applicable
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Comments

Yang Li - Dec. 9, 2010, 8:14 a.m.
From: Forrest Shi <b29237@freescale.com>

Fixed fsl dma slow issue by initializing dma mode register with
bandwidth control. It boosts dma performance and should works
with 85xx board.

Signed-off-by: Forrest Shi <b29237@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 drivers/dma/fsldma.c |    6 ++++--
 drivers/dma/fsldma.h |    9 ++++++++-
 2 files changed, 12 insertions(+), 3 deletions(-)
Dan Williams - Dec. 13, 2010, 10:02 p.m.
On Thu, Dec 9, 2010 at 12:14 AM, Li Yang <leoli@freescale.com> wrote:
> From: Forrest Shi <b29237@freescale.com>
>
> Fixed fsl dma slow issue by initializing dma mode register with
> bandwidth control. It boosts dma performance and should works
> with 85xx board.
>
> Signed-off-by: Forrest Shi <b29237@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>

Applied.

Patch

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 286c3ac..e5e172d 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -50,9 +50,11 @@  static void dma_init(struct fsldma_chan *chan)
 		 * EIE - Error interrupt enable
 		 * EOSIE - End of segments interrupt enable (basic mode)
 		 * EOLNIE - End of links interrupt enable
+		 * BWC - Bandwidth sharing among channels
 		 */
-		DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
-				| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
+		DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
+				| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
+				| FSL_DMA_MR_EOSIE, 32);
 		break;
 	case FSL_DMA_IP_83XX:
 		/* Set the channel to below modes:
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index cb4d6ff..ba9f403 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -1,5 +1,5 @@ 
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author:
  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -36,6 +36,13 @@ 
 #define FSL_DMA_MR_DAHE		0x00002000
 #define FSL_DMA_MR_SAHE		0x00001000
 
+/*
+ * Bandwidth/pause control determines how many bytes a given
+ * channel is allowed to transfer before the DMA engine pauses
+ * the current channel and switches to the next channel
+ */
+#define FSL_DMA_MR_BWC         0x08000000
+
 /* Special MR definition for MPC8349 */
 #define FSL_DMA_MR_EOTIE	0x00000080
 #define FSL_DMA_MR_PRC_RM	0x00000800