From patchwork Thu Dec 9 06:08:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Lin Tang X-Patchwork-Id: 74852 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 8455AB6EDF for ; Thu, 9 Dec 2010 17:08:16 +1100 (EST) Received: (qmail 16824 invoked by alias); 9 Dec 2010 06:08:13 -0000 Received: (qmail 16802 invoked by uid 22791); 9 Dec 2010 06:08:12 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 09 Dec 2010 06:08:07 +0000 Received: (qmail 15657 invoked from network); 9 Dec 2010 06:08:05 -0000 Received: from unknown (HELO ?192.168.1.16?) (cltang@127.0.0.2) by mail.codesourcery.com with ESMTPA; 9 Dec 2010 06:08:05 -0000 Message-ID: <4D007252.7060102@codesourcery.com> Date: Thu, 09 Dec 2010 14:08:18 +0800 From: Chung-Lin Tang User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: gcc-patches Subject: [PATCH, ARM] Fix PR44557, Thumb-1 ICE X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, this patch fixes the ICE in PR44557. It now occurs on trunk only under quite specific option conditions, but debugging this PR leaded to quite obvious Thumb-1 fixes. Also added a simplified testcase, derived from the one on bugzilla. Tested without regressions, okay to commit to trunk? Thanks, Chung-Lin 2010-12-09 Chung-Lin Tang PR target/44557 * config/arm/arm.h (PREFERRED_RELOAD_CLASS): Add CORE_REGS to Thumb-1 return LO_REGS case. * config/arm/arm.md (reload_inhi): Change scratch constraint from 'r' to 'l'. testsuite/ * gcc.target/arm/pr44557.c: New. Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 167626) +++ gcc/config/arm/arm.h (working copy) @@ -1207,6 +1207,7 @@ (TARGET_32BIT ? (CLASS) : \ ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ + || (CLASS) == CORE_REGS \ ? LO_REGS : (CLASS))) /* Must leave BASE_REGS reloads alone */ Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 167626) +++ gcc/config/arm/arm.md (working copy) @@ -5850,7 +5850,7 @@ (define_expand "reload_inhi" [(parallel [(match_operand:HI 0 "s_register_operand" "=r") (match_operand:HI 1 "arm_reload_memory_operand" "o") - (match_operand:DI 2 "s_register_operand" "=&r")])] + (match_operand:DI 2 "s_register_operand" "=&l")])] "TARGET_EITHER" " if (TARGET_ARM) Index: gcc/testsuite/gcc.target/arm/pr44557.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr44557.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr44557.c (revision 0) @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O1 -march=armv5te -fno-omit-frame-pointer -fno-forward-propagate" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +struct S +{ + short x, y; +}; + +void foo (struct S *p, struct S *q, char *t, int n) +{ + struct S *c, d; + int x = 1; + + while (n--) + { + if (*t && p) + c = p; + q->x = d.x + c->x + c->y; + if (x) + { + x = 0; + d.x += c->x; + } + } +}