@@ -2210,6 +2210,20 @@ static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
pcms->pit = value;
}
+static bool pc_machine_get_pam(Object *obj, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+
+ return pcms->pam;
+}
+
+static void pc_machine_set_pam(Object *obj, bool value, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+
+ pcms->pam = value;
+}
+
static void pc_machine_initfn(Object *obj)
{
PCMachineState *pcms = PC_MACHINE(obj);
@@ -2224,6 +2238,7 @@ static void pc_machine_initfn(Object *obj)
pcms->smbus = true;
pcms->sata = true;
pcms->pit = true;
+ pcms->pam = true;
}
static void pc_machine_reset(void)
@@ -2372,6 +2387,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
object_class_property_add_bool(oc, PC_MACHINE_PIT,
pc_machine_get_pit, pc_machine_set_pit, &error_abort);
+
+ object_class_property_add_bool(oc, PC_MACHINE_PAM,
+ pc_machine_get_pam, pc_machine_set_pam, &error_abort);
}
static const TypeInfo pc_machine_info = {
@@ -152,16 +152,18 @@ static void i440fx_update_smram(PCII440FXState *d)
static void i440fx_update_pam(PCII440FXState *d)
{
- int i;
- PCIDevice *pd = PCI_DEVICE(d);
- memory_region_transaction_begin();
- pam_update(&d->pam_regions[0], 0,
- pd->config[I440FX_PAM]);
- for (i = 1; i < 13; i++) {
- pam_update(&d->pam_regions[i], i,
- pd->config[I440FX_PAM + ((i + 1) / 2)]);
+ if (PC_MACHINE(current_machine)->pam) {
+ int i;
+ PCIDevice *pd = PCI_DEVICE(d);
+ memory_region_transaction_begin();
+ pam_update(&d->pam_regions[0], 0,
+ pd->config[I440FX_PAM]);
+ for (i = 1; i < 13; i++) {
+ pam_update(&d->pam_regions[i], i,
+ pd->config[I440FX_PAM + ((i + 1) / 2)]);
+ }
+ memory_region_transaction_commit();
}
- memory_region_transaction_commit();
}
static void i440fx_update_memory_mappings(PCII440FXState *d)
@@ -173,14 +175,16 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
static void i440fx_init_pam(PCII440FXState *d)
{
- int i;
- init_pam(DEVICE(d), d->ram_memory, d->system_memory,
- d->pci_address_space, &d->pam_regions[0],
- PAM_BIOS_BASE, PAM_BIOS_SIZE);
- for (i = 0; i < 12; ++i) {
+ if (PC_MACHINE(current_machine)->pam) {
+ int i;
init_pam(DEVICE(d), d->ram_memory, d->system_memory,
- d->pci_address_space, &d->pam_regions[i + 1],
- PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
+ d->pci_address_space, &d->pam_regions[0],
+ PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ for (i = 0; i < 12; ++i) {
+ init_pam(DEVICE(d), d->ram_memory, d->system_memory,
+ d->pci_address_space, &d->pam_regions[i + 1],
+ PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
+ }
}
}
@@ -310,15 +310,17 @@ static void mch_update_pciexbar(MCHPCIState *mch)
/* PAM */
static void mch_update_pam(MCHPCIState *mch)
{
- PCIDevice *pd = PCI_DEVICE(mch);
- int i;
-
- memory_region_transaction_begin();
- for (i = 0; i < 13; i++) {
- pam_update(&mch->pam_regions[i], i,
- pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
+ if (PC_MACHINE(current_machine)->pam) {
+ PCIDevice *pd = PCI_DEVICE(mch);
+ int i;
+
+ memory_region_transaction_begin();
+ for (i = 0; i < 13; i++) {
+ pam_update(&mch->pam_regions[i], i,
+ pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
+ }
+ memory_region_transaction_commit();
}
- memory_region_transaction_commit();
}
/* SMRAM */
@@ -462,14 +464,16 @@ static void mch_reset(DeviceState *qdev)
static void mch_init_pam(MCHPCIState *mch)
{
- int i;
- init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
- mch->pci_address_space, &mch->pam_regions[0],
- PAM_BIOS_BASE, PAM_BIOS_SIZE);
- for (i = 0; i < 12; ++i) {
+ if (PC_MACHINE(current_machine)->pam) {
+ int i;
init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
- mch->pci_address_space, &mch->pam_regions[i + 1],
- PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
+ mch->pci_address_space, &mch->pam_regions[0],
+ PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ for (i = 0; i < 12; ++i) {
+ init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
+ mch->pci_address_space, &mch->pam_regions[i + 1],
+ PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
+ }
}
}
@@ -66,6 +66,7 @@ struct PCMachineState {
bool smbus;
bool sata;
bool pit;
+ bool pam;
/* RAM information (sizes, addresses, configuration): */
ram_addr_t below_4g_mem_size, above_4g_mem_size;
@@ -93,6 +94,7 @@ struct PCMachineState {
#define PC_MACHINE_SMBUS "smbus"
#define PC_MACHINE_SATA "sata"
#define PC_MACHINE_PIT "pit"
+#define PC_MACHINE_PAM "pam"
/**
* PCMachineClass:
by default PAM is enabled. when PAM is disabled, *_init_pam and *_update_pam are dummy functions Signed-off-by: Anthony Xu <anthony.xu@intel.com> --- hw/i386/pc.c | 18 ++++++++++++++++++ hw/pci-host/piix.c | 36 ++++++++++++++++++++---------------- hw/pci-host/q35.c | 34 +++++++++++++++++++--------------- include/hw/i386/pc.h | 2 ++ 4 files changed, 59 insertions(+), 31 deletions(-)