From patchwork Thu Dec 9 02:55:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 74841 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 21694B70A4 for ; Thu, 9 Dec 2010 13:57:40 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A62C281A2; Thu, 9 Dec 2010 03:56:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id te0KSpYjD16J; Thu, 9 Dec 2010 03:56:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1AA4228178; Thu, 9 Dec 2010 03:56:38 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0716D281CB for ; Thu, 9 Dec 2010 03:56:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iDAxEHH6QKGC for ; Thu, 9 Dec 2010 03:56:33 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from VA3EHSOBE001.bigfish.com (va3ehsobe001.messaging.microsoft.com [216.32.180.11]) by theia.denx.de (Postfix) with ESMTPS id 052BD281A7 for ; Thu, 9 Dec 2010 03:56:04 +0100 (CET) Received: from mail34-va3-R.bigfish.com (10.7.14.250) by VA3EHSOBE001.bigfish.com (10.7.40.21) with Microsoft SMTP Server id 14.1.225.8; Thu, 9 Dec 2010 02:56:02 +0000 Received: from mail34-va3 (localhost.localdomain [127.0.0.1]) by mail34-va3-R.bigfish.com (Postfix) with ESMTP id 75A6A18C02E2 for ; Thu, 9 Dec 2010 02:56:02 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:az33egw01.freescale.net; RD:az33egw01.freescale.net; EFVD:NLI Received: from mail34-va3 (localhost.localdomain [127.0.0.1]) by mail34-va3 (MessageSwitch) id 129186336249353_12948; Thu, 9 Dec 2010 02:56:02 +0000 (UTC) Received: from VA3EHSMHS027.bigfish.com (unknown [10.7.14.236]) by mail34-va3.bigfish.com (Postfix) with ESMTP id 883C3E004B for ; Thu, 9 Dec 2010 02:56:01 +0000 (UTC) Received: from az33egw01.freescale.net (192.88.158.102) by VA3EHSMHS027.bigfish.com (10.7.99.37) with Microsoft SMTP Server (TLS) id 14.1.225.8; Thu, 9 Dec 2010 02:55:59 +0000 Received: from az33smr02.freescale.net (az33smr02.freescale.net [10.64.34.200]) by az33egw01.freescale.net (8.14.3/8.14.3) with ESMTP id oB92toOB017908 for ; Wed, 8 Dec 2010 19:55:57 -0700 (MST) Received: from localhost.localdomain (mvp-10-214-72-131.am.freescale.net [10.214.72.131]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id oB92tg6l025877; Wed, 8 Dec 2010 20:55:49 -0600 (CST) From: York Sun To: Date: Wed, 8 Dec 2010 18:55:38 -0800 Message-ID: <1291863340-4354-8-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1291863340-4354-1-git-send-email-yorksun@freescale.com> References: <1291863340-4354-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH 08/10] Implement workaround for erratum DDRA003 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Erratum DDRA003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 53 ++++++++++++++++++++++++++++++++++- include/configs/P4080DS.h | 1 + 2 files changed, 53 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 568f9f4..0815ba4 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -108,6 +108,55 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); out_be32(&ddr->sdram_cfg, temp_sdram_cfg); +#ifdef CONFIG_SYS_P4080_ERRATUM_DDRA003 + if (regs->ddr_sdram_rcw_2 & 0x00f00000) { + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); + out_be32(&ddr->debug[2], 0x00000400); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); + out_be32(&ddr->mtcr, 0); + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)); + + switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { + case 0x00000000: + out_be32(&ddr->sdram_md_cntl, 0xc4080002); + break; + case 0x00100000: + out_be32(&ddr->sdram_md_cntl, 0xc408000a); + break; + case 0x00200000: + out_be32(&ddr->sdram_md_cntl, 0xc4080012); + break; + case 0x00300000: + out_be32(&ddr->sdram_md_cntl, 0xc408001a); + break; + default: + out_be32(&ddr->sdram_md_cntl, 0xc4080002); + printf("Unsupported RC10\n"); + break; + } + + while (in_be32(&ddr->sdram_md_cntl) & 0x80000000); + udelay(6); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->debug[2], 0x0); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->debug[12], 0x0); + out_be32(&ddr->debug[21], 0x0); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + + } +#endif /* * For 8572 DDR1 erratum - DDR controller may enter illegal state * when operatiing in 32-bit bus mode with 4-beat bursts, @@ -131,8 +180,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, asm volatile("sync;isync"); /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ while (in_be32(&ddr->sdram_cfg_2) & 0x10) { diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index d210016..c19bd39 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -45,6 +45,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPC9 #define CONFIG_SYS_P4080_ERRATUM_DDR1 #define CONFIG_SYS_P4080_ERRATUM_DDR7 +#define CONFIG_SYS_P4080_ERRATUM_DDRA003 #define CONFIG_SYS_P4080_ERRATUM_ESDHC1 #define CONFIG_SYS_P4080_ERRATUM_ESDHC9 #define CONFIG_SYS_P4080_ERRATUM_ESDHC11