From patchwork Thu Dec 9 01:12:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tirumala Marri X-Patchwork-Id: 74823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6E5D3B70A9 for ; Thu, 9 Dec 2010 13:03:45 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EF94E28186; Thu, 9 Dec 2010 03:03:41 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8QJ7oc+VWbSm; Thu, 9 Dec 2010 03:03:41 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 63ED328187; Thu, 9 Dec 2010 03:03:39 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4713128187 for ; Thu, 9 Dec 2010 03:03:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mMTPtC-1NRED for ; Thu, 9 Dec 2010 03:03:33 +0100 (CET) X-Greylist: delayed 3075 seconds by postgrey-1.27 at theia; Thu, 09 Dec 2010 03:03:31 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from denmail01.apm.COM (denmail01-v4020.amcc.com [192.195.68.30]) by theia.denx.de (Postfix) with ESMTPS id 0724F28186 for ; Thu, 9 Dec 2010 03:03:31 +0100 (CET) Received: from amcc.com (svdcld03.amcc.com [10.66.16.94]) by denmail01.apm.COM (8.13.8/8.13.8) with ESMTP id oB91C7R0025322; Wed, 8 Dec 2010 17:12:08 -0800 Received: (from tmarri@localhost) by amcc.com (8.13.1/8.12.2/Submit) id oB91C7T7003292; Wed, 8 Dec 2010 17:12:07 -0800 From: tmarri@apm.com To: u-boot@lists.denx.de Date: Wed, 8 Dec 2010 17:12:07 -0800 Message-Id: <1291857127-3265-1-git-send-email-tmarri@apm.com> X-Mailer: git-send-email 1.6.1.rc3 Cc: sr@denx.de Subject: [U-Boot] [PATCH] ppc4xx: 460SX Eegier board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Tirumala Marri Adding Eiger board support for 460SX SoC. Signed-off-by: Tirumala R Marri --- MAINTAINERS | 4 + board/amcc/eiger/Makefile | 48 +++++++++++ board/amcc/eiger/config.mk | 30 +++++++ board/amcc/eiger/eiger.c | 91 +++++++++++++++++++++ board/amcc/eiger/init.S | 67 +++++++++++++++ boards.cfg | 1 + include/configs/eiger.h | 192 ++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 433 insertions(+), 0 deletions(-) create mode 100644 board/amcc/eiger/Makefile create mode 100644 board/amcc/eiger/config.mk create mode 100644 board/amcc/eiger/eiger.c create mode 100644 board/amcc/eiger/init.S create mode 100644 include/configs/eiger.h diff --git a/MAINTAINERS b/MAINTAINERS index f47fca5..9012092 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -310,6 +310,10 @@ Tirumala Marri bluestone APM821XX +Tirumala Marri + + eiger 460SX + Reinhard Meyer TOP860 MPC860T diff --git a/board/amcc/eiger/Makefile b/board/amcc/eiger/Makefile new file mode 100644 index 0000000..a381de0 --- /dev/null +++ b/board/amcc/eiger/Makefile @@ -0,0 +1,48 @@ +# Adding Makefile for Eiger board +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Authors: Tirumala R Marri +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################## diff --git a/board/amcc/eiger/config.mk b/board/amcc/eiger/config.mk new file mode 100644 index 0000000..aa6cbda --- /dev/null +++ b/board/amcc/eiger/config.mk @@ -0,0 +1,30 @@ +# Adding config.mk for Eiger board +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Authors: Tirumala R Marri +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/eiger/eiger.c b/board/amcc/eiger/eiger.c new file mode 100644 index 0000000..d5b569d --- /dev/null +++ b/board/amcc/eiger/eiger.c @@ -0,0 +1,91 @@ +/* + * Adding board support for Eiger board + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +/* + * UBOOT initiated board specific function calls + */ + +int board_early_init_f(void) +{ + /* + * Setup for UIC on 460SX eiger board + */ + mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted + * cascade to be checked */ + mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical + * interrupts */ + mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: eiger - AMCC 460SX Reference Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} diff --git a/board/amcc/eiger/init.S b/board/amcc/eiger/init.S new file mode 100644 index 0000000..bca56c0 --- /dev/null +++ b/board/amcc/eiger/init.S @@ -0,0 +1,67 @@ +/* + * init.S for Eiger board. + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + .section .bootpg,"ax" + .globl tlbtab +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + /* Although 512 KB, map 256k at a time */ + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I) + + tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) + + /* + * Peripheral base + */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG) +#ifdef CONFIG_PCI + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG) +#endif + tlbtab_end diff --git a/boards.cfg b/boards.cfg index 2209676..c3f9c9c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -641,6 +641,7 @@ bubinga powerpc ppc4xx - amcc canyonlands powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS canyonlands_nand powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 ebony powerpc ppc4xx - amcc +eiger powerpc ppc4xx - amcc glacier powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER glacier_nand powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 haleakala powerpc ppc4xx kilauea amcc - kilauea:HALEAKALA diff --git a/include/configs/eiger.h b/include/configs/eiger.h new file mode 100644 index 0000000..bc082a6 --- /dev/null +++ b/include/configs/eiger.h @@ -0,0 +1,192 @@ +/* + * eiger.h - configuration for Eiger(460SX) Board. + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC460 family */ +#define CONFIG_460SX 1 /* ... PPC460 family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#define CONFIG_SYS_TEXT_BASE 0xfffb0000 + +/* + * Include common defines/options for all AMCC boards + */ +#define CONFIG_HOSTNAME eiger + +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 +#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ +#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x01000000 + +#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000 +#define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000 +#define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000 +#define CONFIG_SYS_PCIE2_CFGBASE 0xba000000 + +/* PCIe mapped UTL registers */ +#define CONFIG_SYS_PCIE0_REGBASE 0xd0000000 +#define CONFIG_SYS_PCIE1_REGBASE 0xd0010000 +#define CONFIG_SYS_PCIE2_REGBASE 0xd0020000 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ + +/* + * Initial RAM & stack pointer (placed in internal SRAM) + */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) + +/* + * DDR SDRAM + */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +#define CONFIG_SYS_SPD_MAX_DIMMS 2 + +/* SPD i2c spd addresses */ +#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR} +#define IIC0_DIMM0_ADDR 0x50 +#define IIC0_DIMM1_ADDR 0x51 + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#define IIC0_BOOTPROM_ADDR 0x52 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +/* + * Flash + */ +#define CONFIG_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 518 +/* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +/* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 +/* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_M88E1141_PHY 1 /* Enable phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_2048PERCLK | \ + EBC_CFG_ATC_HI | \ + EBC_CFG_DTC_HI | \ + EBC_CFG_CTC_HI | \ + EBC_CFG_OEO_PREVIOUS) +/* NOR Flash */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(64) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(2) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +/* Peripheral Bank Configuration Register - EBC_BxCR */ +#define CONFIG_SYS_EBC_PB0CR \ + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +#endif /* __CONFIG_H */