From patchwork Fri Apr 7 09:34:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 748148 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vzvzk5ZT1z9s8B for ; Fri, 7 Apr 2017 19:53:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751738AbdDGJxh (ORCPT ); Fri, 7 Apr 2017 05:53:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16438 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756569AbdDGJxB (ORCPT ); Fri, 7 Apr 2017 05:53:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 07 Apr 2017 02:53:09 -0700 Received: from HQMAIL106.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 07 Apr 2017 02:52:59 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 07 Apr 2017 02:52:59 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Fri, 7 Apr 2017 09:52:59 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Fri, 7 Apr 2017 09:52:55 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Fri, 7 Apr 2017 09:52:52 +0000 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH V3 4/4] pwm: tegra: Add support to configure pin state in suspends/resume Date: Fri, 7 Apr 2017 15:04:02 +0530 Message-ID: <1491557642-15940-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1491557642-15940-1-git-send-email-ldewangan@nvidia.com> References: <1491557642-15940-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan Acked-by: Jon Hunter --- Changes from v1: - Use standard pinctrl names for sleep and active state. - Use API pinctrl_pm_select_*() Changes from V2: - Use returns of pinctrl_pm_select_*() - Rephrase commit message. --- drivers/pwm/pwm-tegra.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 21518be..9c7f180 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -255,6 +256,18 @@ static int tegra_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } +#ifdef CONFIG_PM_SLEEP +static int tegra_pwm_suspend(struct device *dev) +{ + return pinctrl_pm_select_sleep_state(dev); +} + +static int tegra_pwm_resume(struct device *dev) +{ + return pinctrl_pm_select_default_state(dev); +} +#endif + static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, }; @@ -271,10 +284,15 @@ static const struct of_device_id tegra_pwm_of_match[] = { MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); +static const struct dev_pm_ops tegra_pwm_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume) +}; + static struct platform_driver tegra_pwm_driver = { .driver = { .name = "tegra-pwm", .of_match_table = tegra_pwm_of_match, + .pm = &tegra_pwm_pm_ops, }, .probe = tegra_pwm_probe, .remove = tegra_pwm_remove,