From patchwork Fri Apr 7 00:16:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 747997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vzgCJ25nbz9s8P for ; Fri, 7 Apr 2017 10:18:04 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vzgCJ126mzDqKY for ; Fri, 7 Apr 2017 10:18:04 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vzgBr02ynzDqHj for ; Fri, 7 Apr 2017 10:17:39 +1000 (AEST) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v370Dbcr111622 for ; Thu, 6 Apr 2017 20:17:31 -0400 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0a-001b2d01.pphosted.com with ESMTP id 29nugn2j29-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 06 Apr 2017 20:17:31 -0400 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 7 Apr 2017 10:17:24 +1000 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v370HFwf54198298 for ; Fri, 7 Apr 2017 10:17:23 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v370GoxA000473 for ; Fri, 7 Apr 2017 10:16:51 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v370GoKU000306; Fri, 7 Apr 2017 10:16:50 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id D534DA027C; Fri, 7 Apr 2017 10:16:26 +1000 (AEST) Received: from gwshan.ozlabs.ibm.com (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id C959FE3AC4; Fri, 7 Apr 2017 10:16:26 +1000 (AEST) Received: by gwshan.ozlabs.ibm.com (Postfix, from userid 1000) id BFCADAC235E; Fri, 7 Apr 2017 10:16:26 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 7 Apr 2017 10:16:19 +1000 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491524180-12644-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1491524180-12644-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17040700-0044-0000-0000-000002401690 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17040700-0045-0000-0000-000006C66266 Message-Id: <1491524180-12644-4-git-send-email-gwshan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-06_20:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704070001 Subject: [Skiboot] [PATCH 3/4] core/pci: Use cached vendor/device/class IDs on populating device node X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This uses the cached vendor/device/class IDs when populating the device node for the particular PCI device, no need to read from the hardware in order to save some CPU cycles. Signed-off-by: Gavin Shan --- core/pci.c | 54 +++++++++++++++++++++++------------------------------- include/pci.h | 3 +++ 2 files changed, 26 insertions(+), 31 deletions(-) diff --git a/core/pci.c b/core/pci.c index a93239b..7742454 100644 --- a/core/pci.c +++ b/core/pci.c @@ -251,7 +251,6 @@ static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *paren pd->vdid = vdid; pci_cfg_read32(phb, bdfn, PCI_CFG_SUBSYS_VENDOR_ID, &pd->sub_vdid); pci_cfg_read32(phb, bdfn, PCI_CFG_REV_ID, &pd->class); - pd->class >>= 8; pd->parent = parent; list_head_init(&pd->pcrf); @@ -268,6 +267,14 @@ static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *paren pci_init_capabilities(phb, pd); + /* + * Quirk for IBM bridge bogus class on PCIe root complex. + * Without it, the PCI DN won't be created for its downstream + * devices in Linux. + */ + if (!parent && pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) + pd->class = (0x06040000 | (pd->class & 0xff)); + /* If it's a bridge, sanitize the bus numbers to avoid forwarding * * This will help when walking down those bridges later on @@ -1331,16 +1338,12 @@ static void pci_add_loc_code(struct dt_node *np, struct pci_device *pd) } static void pci_print_summary_line(struct phb *phb, struct pci_device *pd, - struct dt_node *np, u32 rev_class, - const char *cname) + struct dt_node *np, const char *cname) { const char *label, *dtype, *s; - u32 vdid; #define MAX_SLOTSTR 32 char slotstr[MAX_SLOTSTR + 1] = { 0, }; - pci_cfg_read32(phb, pd->bdfn, 0, &vdid); - /* If it's a slot, it has a slot-label */ label = dt_prop_get_def(np, "ibm,slot-label", NULL); if (label) { @@ -1379,14 +1382,15 @@ static void pci_print_summary_line(struct phb *phb, struct pci_device *pd, if (pd->is_bridge) PCINOTICE(phb, pd->bdfn, "[%s] %04x %04x R:%02x C:%06x B:%02x..%02x %s\n", - dtype, vdid & 0xffff, vdid >> 16, - rev_class & 0xff, rev_class >> 8, pd->secondary_bus, - pd->subordinate_bus, slotstr); + dtype, PCI_VENDOR_ID(pd->vdid), PCI_DEVICE_ID(pd->vdid), + PCI_CLASS_REV(pd->class), PCI_CLASS_CODE(pd->class), + pd->secondary_bus, pd->subordinate_bus, slotstr); else PCINOTICE(phb, pd->bdfn, "[%s] %04x %04x R:%02x C:%06x (%14s) %s\n", - dtype, vdid & 0xffff, vdid >> 16, - rev_class & 0xff, rev_class >> 8, cname, slotstr); + dtype, PCI_VENDOR_ID(pd->vdid), PCI_DEVICE_ID(pd->vdid), + PCI_CLASS_REV(pd->class), PCI_CLASS_CODE(pd->class), + cname, slotstr); } static void pci_add_one_device_node(struct phb *phb, @@ -1400,7 +1404,6 @@ static void pci_add_one_device_node(struct phb *phb, #define MAX_NAME 256 char name[MAX_NAME]; char compat[MAX_NAME]; - uint32_t rev_class, vdid; uint32_t reg[5]; uint8_t intpin; const uint32_t ranges_direct[] = { @@ -1411,19 +1414,8 @@ static void pci_add_one_device_node(struct phb *phb, 0x02000000, 0x0, 0x0, 0xf0000000, 0x0}; - pci_cfg_read32(phb, pd->bdfn, 0, &vdid); - pci_cfg_read32(phb, pd->bdfn, PCI_CFG_REV_ID, &rev_class); pci_cfg_read8(phb, pd->bdfn, PCI_CFG_INT_PIN, &intpin); - - /* - * Quirk for IBM bridge bogus class on PCIe root complex. - * Without it, the PCI DN won't be created for its downstream - * devices in Linux. - */ - if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false) && - parent_node == phb->dt_node) - rev_class = (rev_class & 0xff) | 0x6040000; - cname = pci_class_name(rev_class >> 8); + cname = pci_class_name(PCI_CLASS_CODE(pd->class)); if (pd->bdfn & 0x7) snprintf(name, MAX_NAME - 1, "%s@%x,%x", @@ -1436,17 +1428,17 @@ static void pci_add_one_device_node(struct phb *phb, /* XXX FIXME: make proper "compatible" properties */ if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) { snprintf(compat, MAX_NAME, "pciex%x,%x", - vdid & 0xffff, vdid >> 16); + PCI_VENDOR_ID(pd->vdid), PCI_DEVICE_ID(pd->vdid)); dt_add_property_cells(np, "ibm,pci-config-space-type", 1); } else { snprintf(compat, MAX_NAME, "pci%x,%x", - vdid & 0xffff, vdid >> 16); + PCI_VENDOR_ID(pd->vdid), PCI_DEVICE_ID(pd->vdid)); dt_add_property_cells(np, "ibm,pci-config-space-type", 0); } - dt_add_property_cells(np, "class-code", rev_class >> 8); - dt_add_property_cells(np, "revision-id", rev_class & 0xff); - dt_add_property_cells(np, "vendor-id", vdid & 0xffff); - dt_add_property_cells(np, "device-id", vdid >> 16); + dt_add_property_cells(np, "class-code", PCI_CLASS_CODE(pd->class)); + dt_add_property_cells(np, "revision-id", PCI_CLASS_REV(pd->class)); + dt_add_property_cells(np, "vendor-id", PCI_VENDOR_ID(pd->vdid)); + dt_add_property_cells(np, "device-id", PCI_DEVICE_ID(pd->vdid)); if (intpin) dt_add_property_cells(np, "interrupts", intpin); @@ -1478,7 +1470,7 @@ static void pci_add_one_device_node(struct phb *phb, dt_add_property(np, "reg", reg, sizeof(reg)); /* Print summary info about the device */ - pci_print_summary_line(phb, pd, np, rev_class, cname); + pci_print_summary_line(phb, pd, np, cname); if (!pd->is_bridge) return; diff --git a/include/pci.h b/include/pci.h index 296fb8d..1c13545 100644 --- a/include/pci.h +++ b/include/pci.h @@ -75,6 +75,9 @@ struct pci_device { #define PCI_VENDOR_ID(x) ((x) & 0xFFFF) #define PCI_DEVICE_ID(x) ((x) >> 8) uint32_t class; +#define PCI_CLASS_REV(x) ((x) & 0xFF) +#define PCI_CLASS_CODE(x) ((x) >> 8) +#define PCI_CLASS_ID(x) ((x) >> 16) uint64_t cap_list; struct { uint32_t pos;