From patchwork Wed Dec 8 21:00:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 74779 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C00CBB70A9 for ; Thu, 9 Dec 2010 08:01:03 +1100 (EST) Received: (qmail 1572 invoked by alias); 8 Dec 2010 21:01:01 -0000 Received: (qmail 1563 invoked by uid 22791); 8 Dec 2010 21:00:59 -0000 X-SWARE-Spam-Status: No, hits=-6.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, SPF_HELO_PASS, TW_TV, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 08 Dec 2010 21:00:53 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oB8L0que018371 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 8 Dec 2010 16:00:52 -0500 Received: from tyan-ft48-01.lab.bos.redhat.com (tyan-ft48-01.lab.bos.redhat.com [10.16.42.4]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id oB8L0p9F017262 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 8 Dec 2010 16:00:52 -0500 Received: from tyan-ft48-01.lab.bos.redhat.com (localhost.localdomain [127.0.0.1]) by tyan-ft48-01.lab.bos.redhat.com (8.14.4/8.14.4) with ESMTP id oB8L0p8q032345; Wed, 8 Dec 2010 22:00:51 +0100 Received: (from jakub@localhost) by tyan-ft48-01.lab.bos.redhat.com (8.14.4/8.14.4/Submit) id oB8L0oCn032317; Wed, 8 Dec 2010 22:00:50 +0100 Date: Wed, 8 Dec 2010 22:00:50 +0100 From: Jakub Jelinek To: David Edelsohn Cc: gcc-patches@gcc.gnu.org, Michael Meissner Subject: [PATCH] Fix rs6000 stve* patterns (PR target/41082) Message-ID: <20101208210050.GH29412@tyan-ft48-01.lab.bos.redhat.com> Reply-To: Jakub Jelinek MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi! The where_2.f90 testcase is miscompiled on ppc64-darwin with -O3 -m64 -mtune=power4. The problem is in the altivec_stve* patterns, which is represented as a V4SI mode store to MEM, but with offset already adjusted, so e.g. DSE can believe memory after the end of the V4SI mode temp is killed by the store. Fixed by not using stve*x at all in rs6000_expand_vector_extract (the temp slot is uninitialized and nothing ever looks at the other bytes, so there is no point in avoiding storing other bytes - stvx should work fine) and adjusting the patterns for the vec_stve* intrinsics so that it represents what the insn actually does - stores only one scalar instead of the whole vector. Michael has bootstrapped/regtested this patch on power7. Ok for trunk? 2010-12-08 Jakub Jelinek PR target/41082 * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Use stvx instead of stve*x. (altivec_expand_stv_builtin): For op0 use mode of operand 1 instead of operand 0. * config/rs6000/altivec.md (VI_scalar): New mode attr. (altivec_stvex, *altivec_stvesfx): Use scalar instead of vector mode for operand 0, put operand 1 into UNSPEC. Jakub --- gcc/config/rs6000/rs6000.c.jj 2010-12-02 11:51:30.000000000 +0100 +++ gcc/config/rs6000/rs6000.c 2010-12-08 08:25:40.000000000 +0100 @@ -5436,7 +5436,7 @@ rs6000_expand_vector_extract (rtx target { enum machine_mode mode = GET_MODE (vec); enum machine_mode inner_mode = GET_MODE_INNER (mode); - rtx mem, x; + rtx mem; if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode)) { @@ -5449,17 +5449,11 @@ rs6000_expand_vector_extract (rtx target /* Allocate mode-sized buffer. */ mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); + emit_move_insn (mem, vec); + /* Add offset to field within buffer matching vector element. */ - mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode)); + mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode)); - /* Store single field into mode-sized buffer. */ - x = gen_rtx_UNSPEC (VOIDmode, - gen_rtvec (1, const0_rtx), UNSPEC_STVE); - emit_insn (gen_rtx_PARALLEL (VOIDmode, - gen_rtvec (2, - gen_rtx_SET (VOIDmode, - mem, vec), - x))); emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0)); } @@ -11114,6 +11108,7 @@ altivec_expand_stv_builtin (enum insn_co rtx op2 = expand_normal (arg2); rtx pat, addr; enum machine_mode tmode = insn_data[icode].operand[0].mode; + enum machine_mode smode = insn_data[icode].operand[1].mode; enum machine_mode mode1 = Pmode; enum machine_mode mode2 = Pmode; @@ -11123,8 +11118,8 @@ altivec_expand_stv_builtin (enum insn_co || arg2 == error_mark_node) return const0_rtx; - if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) - op0 = copy_to_mode_reg (tmode, op0); + if (! (*insn_data[icode].operand[1].predicate) (op0, smode)) + op0 = copy_to_mode_reg (smode, op0); op2 = copy_to_mode_reg (mode2, op2); --- gcc/config/rs6000/altivec.md.jj 2010-11-19 20:56:52.000000000 +0100 +++ gcc/config/rs6000/altivec.md 2010-12-08 08:19:21.000000000 +0100 @@ -169,6 +169,7 @@ (define_mode_iterator VM [V4SI V8HI V16Q (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI]) (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")]) +(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")]) ;; Vector move instructions. (define_insn "*altivec_mov" @@ -1775,19 +1776,15 @@ (define_insn "altivec_stvxl" [(set_attr "type" "vecstore")]) (define_insn "altivec_stvex" - [(parallel - [(set (match_operand:VI 0 "memory_operand" "=Z") - (match_operand:VI 1 "register_operand" "v")) - (unspec [(const_int 0)] UNSPEC_STVE)])] + [(set (match_operand: 0 "memory_operand" "=Z") + (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] "TARGET_ALTIVEC" "stvex %1,%y0" [(set_attr "type" "vecstore")]) (define_insn "*altivec_stvesfx" - [(parallel - [(set (match_operand:V4SF 0 "memory_operand" "=Z") - (match_operand:V4SF 1 "register_operand" "v")) - (unspec [(const_int 0)] UNSPEC_STVE)])] + [(set (match_operand:SF 0 "memory_operand" "=Z") + (unspec:SF [(match_operand:V4SF 1 "register_operand" "v")] UNSPEC_STVE))] "TARGET_ALTIVEC" "stvewx %1,%y0" [(set_attr "type" "vecstore")])