From patchwork Wed Apr 5 14:13:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 747344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vypJk6lVBz9s8F for ; Thu, 6 Apr 2017 00:34:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755386AbdDEOdZ (ORCPT ); Wed, 5 Apr 2017 10:33:25 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3765 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753570AbdDEOcW (ORCPT ); Wed, 5 Apr 2017 10:32:22 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 05 Apr 2017 07:52:28 -0700 Received: from HQMAIL101.nvidia.com ([172.20.13.39]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 05 Apr 2017 07:28:54 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 05 Apr 2017 07:28:54 -0700 Received: from BGMAIL104.nvidia.com (10.25.59.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 5 Apr 2017 14:32:20 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by bgmail104.nvidia.com (10.25.59.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 5 Apr 2017 14:32:16 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Wed, 5 Apr 2017 14:32:13 +0000 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation Date: Wed, 5 Apr 2017 19:43:43 +0530 Message-ID: <1491401626-31303-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1491401626-31303-1-git-send-email-ldewangan@nvidia.com> References: <1491401626-31303-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one instead of implementing the same locally. This increase readability. Signed-off-by: Laxman Dewangan --- drivers/pwm/pwm-tegra.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index e464784..0a688da 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -85,8 +85,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * nearest integer during division. */ c *= (1 << PWM_DUTY_WIDTH); - c += period_ns / 2; - do_div(c, period_ns); + c = DIV_ROUND_CLOSEST_ULL(c, period_ns); val = (u32)c << PWM_DUTY_SHIFT;