From patchwork Wed Apr 5 14:13:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 747338 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vypHR1Ts7z9s8F for ; Thu, 6 Apr 2017 00:33:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932632AbdDEOde (ORCPT ); Wed, 5 Apr 2017 10:33:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3798 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754103AbdDEOcb (ORCPT ); Wed, 5 Apr 2017 10:32:31 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 05 Apr 2017 07:52:38 -0700 Received: from HQMAIL107.nvidia.com ([172.20.13.39]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 05 Apr 2017 07:29:03 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 05 Apr 2017 07:29:03 -0700 Received: from BGMAIL104.nvidia.com (10.25.59.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 5 Apr 2017 14:32:29 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by bgmail104.nvidia.com (10.25.59.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 5 Apr 2017 14:32:26 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Wed, 5 Apr 2017 14:32:22 +0000 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Date: Wed, 5 Apr 2017 19:43:45 +0530 Message-ID: <1491401626-31303-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1491401626-31303-1-git-send-email-ldewangan@nvidia.com> References: <1491401626-31303-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. The tristate (high impedance of PWM pin form Tegra) also define one of the state of PWM regulator which needs to be configure in suspend state of system. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan --- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index b4e7377..145c323 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -19,6 +19,19 @@ Required properties: - reset-names: Must include the following entries: - pwm +Optional properties: +============================ +In some of the interface like PWM based regualator device, it is required +to configure the pins diffrently in different states, specially in suspend +state of the system. The configuration of pin is provided via the pinctrl +DT node as detailed in the pinctrl DT binding document + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +The PWM node will have following optional properties. +pinctrl-names: Pin state names. Must be "suspend" and "resume". +pinctrl-0: Node handle of the suspend state configuration of pins. +pinctrl-1: Node handle of the resume state configuration of pins. + Example: pwm: pwm@7000a000 { @@ -29,3 +42,33 @@ Example: resets = <&tegra_car 17>; reset-names = "pwm"; }; + + +Example with the pin configuration for suspend and resume: +========================================================= +Here Pin PE7 is used as PWM. + +#include + + pinmux@70000868 { + pwm_suspend: pwm_suspend_state { + pe7 { + nvidia,pins = "pe7"; + nvidia,tristate = ; + }; + }; + + pwm_resume: pwm_resume_state { + pe7 { + nvidia,pins = "pe7"; + nvidia,tristate = ; + }; + }; + }; + + pwm@7000a000 { + /* Mandatory pwm properties */ + pinctrl-names = "suspend", "resume"; + pinctrl-0 = <&pwm_suspend>; + pinctrl-1 = <&pwm_resume>; + };