| Message ID | 1491396106-26376-4-git-send-email-clg@kaod.org |
|---|---|
| State | New |
| Headers | show |
On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote: > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > It adds the Naples chip which supports proper LPC interrupts via the > LPC controller rather than via an external CPLD. > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > [clg: - updated for qemu-2.9 > - ported on latest PowerNV patchset ] > Signed-off-by: Cédric Le Goater <clg@kaod.org> > Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > hw/ppc/pnv.c | 13 ++++++++++++- > hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++-- > include/hw/ppc/pnv_lpc.h | 9 +++++++++ > 3 files changed, 66 insertions(+), 3 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 24e523f554c6..78133e5d20e1 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) > > static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) > { > - /* XXX TODO */ > + PnvChip *chip = opaque; > + PnvLpcController *lpc = &chip->lpc; > + > + /* The Naples HW latches the 1 levels, clearing is done by SW */ > + if (level) { > + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; > + pnv_lpc_eval_irqs(lpc); > + } > } Now that you have a more complete LPC model, I think this function, and the allocation of the LPC irqs should move into pnv_lpc.c. Apart from that, looks fine. > > static ISABus *pnv_isa_create(PnvChip *chip) > @@ -699,6 +706,10 @@ static void pnv_chip_init(Object *obj) > object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); > object_property_add_const_link(OBJECT(&chip->occ), "psi", > OBJECT(&chip->psi), &error_abort); > + > + /* The LPC controller needs PSI to generate interrupts */ > + object_property_add_const_link(OBJECT(&chip->lpc), "psi", > + OBJECT(&chip->psi), &error_abort); > } > > static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) > diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c > index 78db52415b11..20cbb6a0dbbd 100644 > --- a/hw/ppc/pnv_lpc.c > +++ b/hw/ppc/pnv_lpc.c > @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = { > .endianness = DEVICE_BIG_ENDIAN, > }; > > +void pnv_lpc_eval_irqs(PnvLpcController *lpc) > +{ > + bool lpc_to_opb_irq = false; > + > + /* Update LPC controller to OPB line */ > + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { > + uint32_t irqs; > + > + irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; > + lpc_to_opb_irq = (irqs != 0); > + } > + > + /* We don't honor the polarity register, it's pointless and unused > + * anyway > + */ > + if (lpc_to_opb_irq) { > + lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; > + } else { > + lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; > + } > + > + /* Update OPB internal latch */ > + lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; > + > + /* Reflect the interrupt */ > + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0); > +} > + > static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) > { > PnvLpcController *lpc = opaque; > @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, > break; > case LPC_HC_IRQSER_CTRL: > lpc->lpc_hc_irqser_ctrl = val; > + pnv_lpc_eval_irqs(lpc); > break; > case LPC_HC_IRQMASK: > lpc->lpc_hc_irqmask = val; > + pnv_lpc_eval_irqs(lpc); > break; > case LPC_HC_IRQSTAT: > lpc->lpc_hc_irqstat &= ~val; > + pnv_lpc_eval_irqs(lpc); > break; > case LPC_HC_ERROR_ADDRESS: > break; > @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr, > switch (addr) { > case OPB_MASTER_LS_IRQ_STAT: > lpc->opb_irq_stat &= ~val; > + pnv_lpc_eval_irqs(lpc); > break; > case OPB_MASTER_LS_IRQ_MASK: > - /* XXX Filter out reserved bits */ > lpc->opb_irq_mask = val; > + pnv_lpc_eval_irqs(lpc); > break; > case OPB_MASTER_LS_IRQ_POL: > - /* XXX Filter out reserved bits */ > lpc->opb_irq_pol = val; > + pnv_lpc_eval_irqs(lpc); > break; > case OPB_MASTER_LS_IRQ_INPUT: > /* Read only */ > @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = { > static void pnv_lpc_realize(DeviceState *dev, Error **errp) > { > PnvLpcController *lpc = PNV_LPC(dev); > + Object *obj; > + Error *error = NULL; > > /* Reg inits */ > lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; > @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) > pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), > &pnv_lpc_xscom_ops, lpc, "xscom-lpc", > PNV_XSCOM_LPC_SIZE); > + > + /* get PSI object from chip */ > + obj = object_property_get_link(OBJECT(dev), "psi", &error); > + if (!obj) { > + error_setg(errp, "%s: required link 'psi' not found: %s", > + __func__, error_get_pretty(error)); > + return; > + } > + lpc->psi = PNV_PSI(obj); > } > > static void pnv_lpc_class_init(ObjectClass *klass, void *data) > diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h > index 38e5506975aa..53040026c37b 100644 > --- a/include/hw/ppc/pnv_lpc.h > +++ b/include/hw/ppc/pnv_lpc.h > @@ -23,6 +23,8 @@ > #define PNV_LPC(obj) \ > OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) > > +typedef struct PnvPsi PnvPsi; > + > typedef struct PnvLpcController { > DeviceState parent; > > @@ -62,6 +64,13 @@ typedef struct PnvLpcController { > > /* XSCOM registers */ > MemoryRegion xscom_regs; > + > + /* PSI to generate interrupts */ > + PnvPsi *psi; > } PnvLpcController; > > +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ > + > +void pnv_lpc_eval_irqs(PnvLpcController *lpc); > + > #endif /* _PPC_PNV_LPC_H */
On 04/06/2017 04:02 AM, David Gibson wrote: > On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org> >> >> It adds the Naples chip which supports proper LPC interrupts via the >> LPC controller rather than via an external CPLD. >> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> >> [clg: - updated for qemu-2.9 >> - ported on latest PowerNV patchset ] >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> >> --- >> hw/ppc/pnv.c | 13 ++++++++++++- >> hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++-- >> include/hw/ppc/pnv_lpc.h | 9 +++++++++ >> 3 files changed, 66 insertions(+), 3 deletions(-) >> >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index 24e523f554c6..78133e5d20e1 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) >> >> static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) >> { >> - /* XXX TODO */ >> + PnvChip *chip = opaque; >> + PnvLpcController *lpc = &chip->lpc; >> + >> + /* The Naples HW latches the 1 levels, clearing is done by SW */ >> + if (level) { >> + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; >> + pnv_lpc_eval_irqs(lpc); >> + } >> } > > Now that you have a more complete LPC model, I think this function, > and the allocation of the LPC irqs should move into pnv_lpc.c. I agree it would look better. I have introduced a pnv_lpc_isa_irq_create() in next version. Thanks, C. > > Apart from that, looks fine. > >> >> static ISABus *pnv_isa_create(PnvChip *chip) >> @@ -699,6 +706,10 @@ static void pnv_chip_init(Object *obj) >> object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); >> object_property_add_const_link(OBJECT(&chip->occ), "psi", >> OBJECT(&chip->psi), &error_abort); >> + >> + /* The LPC controller needs PSI to generate interrupts */ >> + object_property_add_const_link(OBJECT(&chip->lpc), "psi", >> + OBJECT(&chip->psi), &error_abort); >> } >> >> static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) >> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c >> index 78db52415b11..20cbb6a0dbbd 100644 >> --- a/hw/ppc/pnv_lpc.c >> +++ b/hw/ppc/pnv_lpc.c >> @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = { >> .endianness = DEVICE_BIG_ENDIAN, >> }; >> >> +void pnv_lpc_eval_irqs(PnvLpcController *lpc) >> +{ >> + bool lpc_to_opb_irq = false; >> + >> + /* Update LPC controller to OPB line */ >> + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { >> + uint32_t irqs; >> + >> + irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; >> + lpc_to_opb_irq = (irqs != 0); >> + } >> + >> + /* We don't honor the polarity register, it's pointless and unused >> + * anyway >> + */ >> + if (lpc_to_opb_irq) { >> + lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; >> + } else { >> + lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; >> + } >> + >> + /* Update OPB internal latch */ >> + lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; >> + >> + /* Reflect the interrupt */ >> + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0); >> +} >> + >> static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) >> { >> PnvLpcController *lpc = opaque; >> @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, >> break; >> case LPC_HC_IRQSER_CTRL: >> lpc->lpc_hc_irqser_ctrl = val; >> + pnv_lpc_eval_irqs(lpc); >> break; >> case LPC_HC_IRQMASK: >> lpc->lpc_hc_irqmask = val; >> + pnv_lpc_eval_irqs(lpc); >> break; >> case LPC_HC_IRQSTAT: >> lpc->lpc_hc_irqstat &= ~val; >> + pnv_lpc_eval_irqs(lpc); >> break; >> case LPC_HC_ERROR_ADDRESS: >> break; >> @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr, >> switch (addr) { >> case OPB_MASTER_LS_IRQ_STAT: >> lpc->opb_irq_stat &= ~val; >> + pnv_lpc_eval_irqs(lpc); >> break; >> case OPB_MASTER_LS_IRQ_MASK: >> - /* XXX Filter out reserved bits */ >> lpc->opb_irq_mask = val; >> + pnv_lpc_eval_irqs(lpc); >> break; >> case OPB_MASTER_LS_IRQ_POL: >> - /* XXX Filter out reserved bits */ >> lpc->opb_irq_pol = val; >> + pnv_lpc_eval_irqs(lpc); >> break; >> case OPB_MASTER_LS_IRQ_INPUT: >> /* Read only */ >> @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = { >> static void pnv_lpc_realize(DeviceState *dev, Error **errp) >> { >> PnvLpcController *lpc = PNV_LPC(dev); >> + Object *obj; >> + Error *error = NULL; >> >> /* Reg inits */ >> lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; >> @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) >> pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), >> &pnv_lpc_xscom_ops, lpc, "xscom-lpc", >> PNV_XSCOM_LPC_SIZE); >> + >> + /* get PSI object from chip */ >> + obj = object_property_get_link(OBJECT(dev), "psi", &error); >> + if (!obj) { >> + error_setg(errp, "%s: required link 'psi' not found: %s", >> + __func__, error_get_pretty(error)); >> + return; >> + } >> + lpc->psi = PNV_PSI(obj); >> } >> >> static void pnv_lpc_class_init(ObjectClass *klass, void *data) >> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h >> index 38e5506975aa..53040026c37b 100644 >> --- a/include/hw/ppc/pnv_lpc.h >> +++ b/include/hw/ppc/pnv_lpc.h >> @@ -23,6 +23,8 @@ >> #define PNV_LPC(obj) \ >> OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) >> >> +typedef struct PnvPsi PnvPsi; >> + >> typedef struct PnvLpcController { >> DeviceState parent; >> >> @@ -62,6 +64,13 @@ typedef struct PnvLpcController { >> >> /* XSCOM registers */ >> MemoryRegion xscom_regs; >> + >> + /* PSI to generate interrupts */ >> + PnvPsi *psi; >> } PnvLpcController; >> >> +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ >> + >> +void pnv_lpc_eval_irqs(PnvLpcController *lpc); >> + >> #endif /* _PPC_PNV_LPC_H */ >
On 04/06/2017 04:02 AM, David Gibson wrote: > On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org> >> >> It adds the Naples chip which supports proper LPC interrupts via the >> LPC controller rather than via an external CPLD. >> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> >> [clg: - updated for qemu-2.9 >> - ported on latest PowerNV patchset ] >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> >> --- >> hw/ppc/pnv.c | 13 ++++++++++++- >> hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++-- >> include/hw/ppc/pnv_lpc.h | 9 +++++++++ >> 3 files changed, 66 insertions(+), 3 deletions(-) >> >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index 24e523f554c6..78133e5d20e1 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) >> >> static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) >> { >> - /* XXX TODO */ >> + PnvChip *chip = opaque; >> + PnvLpcController *lpc = &chip->lpc; >> + >> + /* The Naples HW latches the 1 levels, clearing is done by SW */ >> + if (level) { >> + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; >> + pnv_lpc_eval_irqs(lpc); >> + } >> } > > Now that you have a more complete LPC model, I think this function, > and the allocation of the LPC irqs should move into pnv_lpc.c. > > > Apart from that, looks fine. While I am at changing things, we have a 'cpld_irqstate' under the machine to model the state of the CPLD chip. It is only used in : static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) { PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine()); uint32_t old_state = pnv->cpld_irqstate; PnvLpcController *lpc = opaque; if (level) { pnv->cpld_irqstate |= 1u << n; } else { pnv->cpld_irqstate &= ~(1u << n); } if (pnv->cpld_irqstate != old_state) { pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0); } } May be we could move that under the LPC object even if it is not strictly correct from a HW pov ? Thanks, C.
On Thu, 2017-04-06 at 14:44 +0200, Cédric Le Goater wrote: > May be we could move that under the LPC object even if it is not > strictly > correct from a HW pov ? I'm not fan of this. It's really not part of the LPC controller and it's specific to a certain crop of P8 machines. Cheers, Ben.
On 04/06/2017 11:54 PM, Benjamin Herrenschmidt wrote: > On Thu, 2017-04-06 at 14:44 +0200, Cédric Le Goater wrote: >> May be we could move that under the LPC object even if it is not >> strictly >> correct from a HW pov ? > > I'm not fan of this. It's really not part of the LPC controller and > it's specific to a certain crop of P8 machines. OK Let's keep it there then. no big deal. Thanks, C.
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 24e523f554c6..78133e5d20e1 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) { - /* XXX TODO */ + PnvChip *chip = opaque; + PnvLpcController *lpc = &chip->lpc; + + /* The Naples HW latches the 1 levels, clearing is done by SW */ + if (level) { + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; + pnv_lpc_eval_irqs(lpc); + } } static ISABus *pnv_isa_create(PnvChip *chip) @@ -699,6 +706,10 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); + + /* The LPC controller needs PSI to generate interrupts */ + object_property_add_const_link(OBJECT(&chip->lpc), "psi", + OBJECT(&chip->psi), &error_abort); } static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 78db52415b11..20cbb6a0dbbd 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +void pnv_lpc_eval_irqs(PnvLpcController *lpc) +{ + bool lpc_to_opb_irq = false; + + /* Update LPC controller to OPB line */ + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { + uint32_t irqs; + + irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; + lpc_to_opb_irq = (irqs != 0); + } + + /* We don't honor the polarity register, it's pointless and unused + * anyway + */ + if (lpc_to_opb_irq) { + lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; + } else { + lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; + } + + /* Update OPB internal latch */ + lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; + + /* Reflect the interrupt */ + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0); +} + static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) { PnvLpcController *lpc = opaque; @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, break; case LPC_HC_IRQSER_CTRL: lpc->lpc_hc_irqser_ctrl = val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQMASK: lpc->lpc_hc_irqmask = val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQSTAT: lpc->lpc_hc_irqstat &= ~val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_ERROR_ADDRESS: break; @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr, switch (addr) { case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &= ~val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_MASK: - /* XXX Filter out reserved bits */ lpc->opb_irq_mask = val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_POL: - /* XXX Filter out reserved bits */ lpc->opb_irq_pol = val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_INPUT: /* Read only */ @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc = PNV_LPC(dev); + Object *obj; + Error *error = NULL; /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); + + /* get PSI object from chip */ + obj = object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + lpc->psi = PNV_PSI(obj); } static void pnv_lpc_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506975aa..53040026c37b 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; @@ -62,6 +64,13 @@ typedef struct PnvLpcController { /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ + +void pnv_lpc_eval_irqs(PnvLpcController *lpc); + #endif /* _PPC_PNV_LPC_H */