From patchwork Wed Dec 8 11:15:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 74712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CD215B6EF0 for ; Thu, 9 Dec 2010 00:08:05 +1100 (EST) Received: from localhost ([127.0.0.1]:56589 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PQIHu-0004bQ-7I for incoming@patchwork.ozlabs.org; Wed, 08 Dec 2010 06:34:22 -0500 Received: from [140.186.70.92] (port=59111 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PQHzW-0002Sq-88 for qemu-devel@nongnu.org; Wed, 08 Dec 2010 06:15:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PQHzU-0003CC-TT for qemu-devel@nongnu.org; Wed, 08 Dec 2010 06:15:22 -0500 Received: from smtp.nokia.com ([147.243.1.47]:53999 helo=mgw-sa01.nokia.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PQHzU-0003Bj-Jb for qemu-devel@nongnu.org; Wed, 08 Dec 2010 06:15:20 -0500 Received: from esdhcp04048.research.nokia.com (esdhcp04048.research.nokia.com [172.21.40.48]) by mgw-sa01.nokia.com (Switch-3.4.3/Switch-3.4.3) with ESMTP id oB8BFHUQ009165 for ; Wed, 8 Dec 2010 13:15:18 +0200 From: =?UTF-8?q?Juha=20Riihim=C3=A4ki?= To: qemu-devel@nongnu.org Date: Wed, 8 Dec 2010 13:15:17 +0200 Message-Id: <2a9faddaab040e9b1655eccf5799ee67833e94ca.1291703787.git.juha.riihimaki@nokia.com> X-Mailer: git-send-email 1.7.3.1 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-Nokia-AV: Clean X-MIME-Autoconverted: from 8bit to quoted-printable by mgw-sa01.nokia.com id oB8BFHUQ009165 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH 2/3] target-arm: correct cp15 c1_sys reset value for cortex-a8 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Mattias Holm Signed-off-by: Juha Riihimäki --- target-arm/helper.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5bcfcf7..7cd6a4e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -109,6 +109,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ + env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V6);