From patchwork Tue Apr 4 13:43:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 746794 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vy9Ds6k2Nz9s8c for ; Tue, 4 Apr 2017 23:44:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753715AbdDDNoE (ORCPT ); Tue, 4 Apr 2017 09:44:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6763 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753272AbdDDNoD (ORCPT ); Tue, 4 Apr 2017 09:44:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 04 Apr 2017 07:03:02 -0700 Received: from HQMAIL105.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Apr 2017 06:43:57 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Apr 2017 06:43:57 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 4 Apr 2017 13:43:56 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Tue, 4 Apr 2017 13:43:56 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.175]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 04 Apr 2017 06:43:56 -0700 From: Mikko Perttunen To: , , , CC: , , , Mikko Perttunen Subject: [PATCH v2 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 Date: Tue, 4 Apr 2017 16:43:37 +0300 Message-ID: <1491313417-25085-3-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1491313417-25085-1-git-send-email-mperttunen@nvidia.com> References: <1491313417-25085-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen --- v2: - Only one regs entry arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 3ea5e6369bc3..c023af0be43d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -347,6 +347,13 @@ reg-names = "pmc", "wake", "aotag", "scratch"; }; + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x3fffff>; + + nvidia,bpmp = <&bpmp>; + }; + sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>;