[v5,5/7] vas: Create device tree node

Submitted by Sukadev Bhattiprolu on April 3, 2017, 8:44 p.m.

Details

Message ID 20170403204444.GA6534@us.ibm.com
State New
Headers show

Commit Message

Sukadev Bhattiprolu April 3, 2017, 8:44 p.m.
Stewart Smith [stewart@linux.vnet.ibm.com] wrote:

> > +static void create_dt_node(struct proc_chip *chip)
> > +{
> > +	struct dt_node *dn;
> > +	uint64_t hvwc_start, uwc_start, win_base;
> > +
> > +	win_base = get_window_base_addr(chip);
> > +	hvwc_start = get_hvwc_mmio_bar(chip->id);
> > +	uwc_start = get_uwc_mmio_bar(chip->id);
> > +
> > +	dn = dt_new_addr(chip->devnode, "vas", win_base);
> 
> Could we please have a compatible property here? The kernel code of
> looking for XSCOM nodes isn't ideal and could break in the future, and
> certainly isn't going to work for, say, PowerVM or KVM guests.
> 
> Also, please add documentation to doc/device-tree as to the device tree
> bindings.

Hi Stewart,

Here is the updated patch with some documenation on the VAS dt entries
and the compatible property.

Thanks,

Sukadev
----
From eb16554fb98538fdfb3b1f56d38aefcbcb87933d Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Date: Wed, 25 Jan 2017 16:05:29 -0800
Subject: [PATCH 1/1] vas: Create device tree node

Create a device tree node for VAS and add properties that Linux
will need to configure/use VAS.

Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---

Changelog[v5]:
	[Stewart Smith] Add a compatible "ibm,vas" property and document
	device tree entries.

	[Michael Neuling] Rather than having separate properties for
	HVWC, UWC and window address, make them all "reg" properties.
---
 core/vas.c              |   22 ++++++++++++++++++++++
 doc/device-tree/vas.rst |   23 +++++++++++++++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree/vas.rst

Comments

Benjamin Herrenschmidt April 24, 2017, 6:15 a.m.
On Mon, 2017-04-03 at 13:44 -0700, Sukadev Bhattiprolu wrote:
>         return 0;
>  
> diff --git a/doc/device-tree/vas.rst b/doc/device-tree/vas.rst
> new file mode 100644
> index 0000000..01bb2e1
> --- /dev/null
> +++ b/doc/device-tree/vas.rst
> @@ -0,0 +1,23 @@
> +Virtual Accelerator Switchboard (VAS)
> +
> +VAS is present in P9 or later processors. In P9, each chip has one
> +instance of VAS. Each instance of VAS is represented by a node in
> +the device tree, under the xsccom node associated with the P9 chip.
> +::
> +
> +  /xscom@<xscom_addr>/vas@<vas_addr>
> +
> +with unique xscom and vas addresses.
> +
> +Each VAS node contains: ::
> +
> +  compatible: "ibm,vas"
> +
> +  reg: contains 6 64-bit values. The first two contain the Hypervisor
> +        Window Context BAR start and length values and the next two
> +        contain the OS/User Window Context BAR start and length values.
> +        The last two contain the "window base address" and "window id
> +        shift" values, which are used to compute the hardware paste
> +        address for a send window on this instance of VAS.
> +
> +  vas-id: unique identifier for each instance of VAS in the system.

This is bogus. You can't have a node with powerbus addresses under
the XSCOM node. Devices below the XSCOM nodes have "reg" properties
that contain XSCOM addresses.

"reg" properties aren't made of arbitrary stuff. They have a well
defined format based on the parent device.

I also object of creating them from init_one_chip(). We shouldn't
be creating devices there.

Instead, look at how we do for other devices that exist both on the
XSCOM bus and the powerbus. We create a device under xscom whose
reg property is the XSCOM base address of the device. This gets done
in the HDAT parsing code.

Then the skiboot code detects those, attaches to them, and in turn
create the powerbus device (mmio) at the *root* of the device-tree
since that represents the powerbus.

Ben.

Patch hide | download patch | download mbox

diff --git a/core/vas.c b/core/vas.c
index 6d475f9..cebd481 100644
--- a/core/vas.c
+++ b/core/vas.c
@@ -256,6 +256,26 @@  static inline uint64_t get_window_base_addr(struct proc_chip *chip)
 	return val;
 }
 
+static void create_dt_node(struct proc_chip *chip)
+{
+	struct dt_node *dn;
+	uint64_t hvwc_start, uwc_start, win_base;
+
+	win_base = get_window_base_addr(chip);
+	hvwc_start = get_hvwc_mmio_bar(chip->id);
+	uwc_start = get_uwc_mmio_bar(chip->id);
+
+	dn = dt_new_addr(chip->devnode, "vas", win_base);
+
+	dt_add_property_strings(dn, "compatible", "ibm,vas");
+
+	dt_add_property_u64s(dn, "reg", hvwc_start, VAS_HVWC_MMIO_BAR_SIZE,
+					uwc_start, VAS_UWC_MMIO_BAR_SIZE,
+					win_base, RMA_LSMP_WINID_SHIFT);
+
+	dt_add_property(dn, "vas-id", &chip->vas_id, sizeof(chip->vas_id));
+}
+
 /*
  * Initialize VAS on one chip
  */
@@ -275,6 +295,8 @@  static int init_one_chip(struct proc_chip *chip)
 	if (init_rma(chip))
 		goto out;
 
+	create_dt_node(chip);
+
 	prlog(PR_INFO, "VAS: Initialized chip %d\n", chip->id);
 	return 0;
 
diff --git a/doc/device-tree/vas.rst b/doc/device-tree/vas.rst
new file mode 100644
index 0000000..01bb2e1
--- /dev/null
+++ b/doc/device-tree/vas.rst
@@ -0,0 +1,23 @@ 
+Virtual Accelerator Switchboard (VAS)
+
+VAS is present in P9 or later processors. In P9, each chip has one
+instance of VAS. Each instance of VAS is represented by a node in
+the device tree, under the xsccom node associated with the P9 chip.
+::
+
+  /xscom@<xscom_addr>/vas@<vas_addr>
+
+with unique xscom and vas addresses.
+
+Each VAS node contains: ::
+
+  compatible: "ibm,vas"
+
+  reg: contains 6 64-bit values. The first two contain the Hypervisor
+        Window Context BAR start and length values and the next two
+        contain the OS/User Window Context BAR start and length values.
+        The last two contain the "window base address" and "window id
+        shift" values, which are used to compute the hardware paste
+        address for a send window on this instance of VAS.
+
+  vas-id: unique identifier for each instance of VAS in the system.