From patchwork Wed Dec 8 08:46:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 74651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8072EB70B8 for ; Wed, 8 Dec 2010 19:48:02 +1100 (EST) Received: from localhost ([127.0.0.1]:58467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PQFgt-0002De-Lg for incoming@patchwork.ozlabs.org; Wed, 08 Dec 2010 03:47:59 -0500 Received: from [140.186.70.92] (port=43006 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PQFfa-0002D8-LR for qemu-devel@nongnu.org; Wed, 08 Dec 2010 03:46:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PQFfW-0000Ye-N2 for qemu-devel@nongnu.org; Wed, 08 Dec 2010 03:46:38 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:47624) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PQFfW-0000Y6-5p for qemu-devel@nongnu.org; Wed, 08 Dec 2010 03:46:34 -0500 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 72D4427FB7; Wed, 8 Dec 2010 17:46:32 +0900 (JST) Received: (nullmailer pid 32031 invoked by uid 1000); Wed, 08 Dec 2010 08:46:28 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Wed, 8 Dec 2010 17:46:26 +0900 Message-Id: <06339af7b6bd68935fd39d3d1d2470fce350f54d.1291797833.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp, mst@redhat.com Subject: [Qemu-devel] [PATTCH v2 4/6] pci/aer: fix interrupt on config write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Michael S. Tsirkin config write handling for aer seems broken: For example, it won't clear a level interrupt when command register is set to 0. Make it match the spec: level should equal the logical or of enabled bits, msi only be sent when the logical or changes. Signed-off-by: Michael S. Tsirkin Signed-off-by: Isaku Yamahata --- - reorder - abort() instead of assert(0) --- hw/pcie_aer.c | 46 +++++++++++++++++----------------------------- 1 files changed, 17 insertions(+), 29 deletions(-) diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c index bc98da0..389e9d5 100644 --- a/hw/pcie_aer.c +++ b/hw/pcie_aer.c @@ -762,43 +762,31 @@ void pcie_aer_root_reset(PCIDevice *dev) */ } -static bool pcie_aer_root_does_trigger(uint32_t cmd, uint32_t status) -{ - return - ((cmd & PCI_ERR_ROOT_CMD_COR_EN) && (status & PCI_ERR_ROOT_COR_RCV)) || - ((cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) && - (status & PCI_ERR_ROOT_NONFATAL_RCV)) || - ((cmd & PCI_ERR_ROOT_CMD_FATAL_EN) && - (status & PCI_ERR_ROOT_FATAL_RCV)); -} - void pcie_aer_root_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len, uint32_t root_cmd_prev) { uint8_t *aer_cap = dev->config + dev->exp.aer_cap; - - /* root command register */ + uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); + uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status); uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); - if (root_cmd & PCI_ERR_ROOT_CMD_EN_MASK) { - /* 6.2.4.1.2 Interrupt Generation */ + /* 6.2.4.1.2 Interrupt Generation */ + if (!msix_enabled(dev) && !msi_enabled(dev)) { + qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd)); + return; + } - /* 0 -> 1 */ - uint32_t root_cmd_set = ~root_cmd_prev & root_cmd; - uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); - bool trigger = pcie_aer_root_does_trigger(root_cmd_set, root_status); + if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) { + /* Send MSI on transition from false to true. */ + return; + } - if (msix_enabled(dev)) { - if (trigger) { - msix_notify(dev, pcie_aer_root_get_vector(dev)); - } - } else if (msi_enabled(dev)) { - if (trigger) { - msi_notify(dev, pcie_aer_root_get_vector(dev)); - } - } else { - qemu_set_irq(dev->irq[dev->exp.aer_intx], trigger); - } + if (msix_enabled(dev)) { + msix_notify(dev, pcie_aer_root_get_vector(dev)); + } else if (msi_enabled(dev)) { + msi_notify(dev, pcie_aer_root_get_vector(dev)); + } else { + abort(); } }