Message ID | 1491231308-15282-2-git-send-email-maddy@linux.vnet.ibm.com (mailing list archive) |
---|---|
State | Changes Requested |
Headers | show |
Hi, > +#define IMC_MAX_CHIPS 32 > +#define IMC_MAX_PMUS 32 > +#define IMC_MAX_PMU_NAME_LEN 256 I've noticed this is used as both the maximum length for event names and event value strings. Would another name suit better? > + > +#define IMC_NEST_MAX_PAGES 16 > + > +#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" > +#define IMC_DTB_NEST_COMPAT "ibm,imc-counters-nest" > + > +/* > + * Structure to hold per chip specific memory address > + * information for nest pmus. Nest Counter data are exported > + * in per-chip reserved memory region by the PORE Engine. > + */ > +struct perchip_nest_info { > + u32 chip_id; > + u64 pbase; > + u64 vbase[IMC_NEST_MAX_PAGES]; > + u64 size; > +}; > + > +/* > + * Place holder for nest pmu events and values. > + */ > +struct imc_events { > + char *ev_name; > + char *ev_value; > +}; > + > +/* > + * Device tree parser code detects IMC pmu support and > + * registers new IMC pmus. This structure will > + * hold the pmu functions and attrs for each imc pmu and > + * will be referenced at the time of pmu registration. > + */ > +struct imc_pmu { > + struct pmu pmu; > + int domain; > + const struct attribute_group *attr_groups[4]; > +}; > + > +/* > + * Domains for IMC PMUs > + */ > +#define IMC_DOMAIN_NEST 1 > +#define IMC_DOMAIN_UNKNOWN -1 > + > +#endif /* PPC_POWERNV_IMC_PMU_DEF_H */ > -- > 2.7.4
On Tuesday 04 April 2017 07:18 AM, Daniel Axtens wrote: > Hi, > >> +#define IMC_MAX_CHIPS 32 >> +#define IMC_MAX_PMUS 32 >> +#define IMC_MAX_PMU_NAME_LEN 256 > I've noticed this is used as both the maximum length for event names and > event value strings. Would another name suit better? This is used in the value string length comparison also. So yes, will change the name to suit better. Thanks for review Maddy > >> + >> +#define IMC_NEST_MAX_PAGES 16 >> + >> +#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" >> +#define IMC_DTB_NEST_COMPAT "ibm,imc-counters-nest" >> + >> +/* >> + * Structure to hold per chip specific memory address >> + * information for nest pmus. Nest Counter data are exported >> + * in per-chip reserved memory region by the PORE Engine. >> + */ >> +struct perchip_nest_info { >> + u32 chip_id; >> + u64 pbase; >> + u64 vbase[IMC_NEST_MAX_PAGES]; >> + u64 size; >> +}; >> + >> +/* >> + * Place holder for nest pmu events and values. >> + */ >> +struct imc_events { >> + char *ev_name; >> + char *ev_value; >> +}; >> + >> +/* >> + * Device tree parser code detects IMC pmu support and >> + * registers new IMC pmus. This structure will >> + * hold the pmu functions and attrs for each imc pmu and >> + * will be referenced at the time of pmu registration. >> + */ >> +struct imc_pmu { >> + struct pmu pmu; >> + int domain; >> + const struct attribute_group *attr_groups[4]; >> +}; >> + >> +/* >> + * Domains for IMC PMUs >> + */ >> +#define IMC_DOMAIN_NEST 1 >> +#define IMC_DOMAIN_UNKNOWN -1 >> + >> +#endif /* PPC_POWERNV_IMC_PMU_DEF_H */ >> -- >> 2.7.4
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> writes: > From: Hemant Kumar <hemant@linux.vnet.ibm.com> > > Create new header file "imc-pmu.h" to add the data structures > and macros needed for IMC pmu support. > > Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> > Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> > Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/imc-pmu.h | 68 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > create mode 100644 arch/powerpc/include/asm/imc-pmu.h > > diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h > new file mode 100644 > index 000000000000..a3d4f1bf9492 > --- /dev/null > +++ b/arch/powerpc/include/asm/imc-pmu.h > @@ -0,0 +1,68 @@ > +#ifndef PPC_POWERNV_IMC_PMU_DEF_H > +#define PPC_POWERNV_IMC_PMU_DEF_H > + > +/* > + * IMC Nest Performance Monitor counter support. > + * > + * Copyright (C) 2016 Madhavan Srinivasan, IBM Corporation. > + * (C) 2016 Hemant K Shaw, IBM Corporation. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#include <linux/perf_event.h> > +#include <linux/slab.h> > +#include <linux/of.h> > +#include <linux/io.h> > +#include <asm/opal.h> > + > +#define IMC_MAX_CHIPS 32 > +#define IMC_MAX_PMUS 32 > +#define IMC_MAX_PMU_NAME_LEN 256 Why do we need a max length? We get the actual lengths from the device tree, so we know at each point in time what the length of any new string should be, right? Otherwise you appear to be, in the general case, using 10x the memory than you could.
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> writes: > +#define IMC_MAX_CHIPS 32 > +#define IMC_MAX_PMUS 32 The max chips and PMUs we'd be able to work out from the device tre though, right? We could just allocate the correct amount of memory on boot. We may hot plug/unplug CPUs, but we're not doing that from a hardware level, what CPUs you get in the DT on PowerNV on boot is all you're getting.
diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h new file mode 100644 index 000000000000..a3d4f1bf9492 --- /dev/null +++ b/arch/powerpc/include/asm/imc-pmu.h @@ -0,0 +1,68 @@ +#ifndef PPC_POWERNV_IMC_PMU_DEF_H +#define PPC_POWERNV_IMC_PMU_DEF_H + +/* + * IMC Nest Performance Monitor counter support. + * + * Copyright (C) 2016 Madhavan Srinivasan, IBM Corporation. + * (C) 2016 Hemant K Shaw, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/perf_event.h> +#include <linux/slab.h> +#include <linux/of.h> +#include <linux/io.h> +#include <asm/opal.h> + +#define IMC_MAX_CHIPS 32 +#define IMC_MAX_PMUS 32 +#define IMC_MAX_PMU_NAME_LEN 256 + +#define IMC_NEST_MAX_PAGES 16 + +#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" +#define IMC_DTB_NEST_COMPAT "ibm,imc-counters-nest" + +/* + * Structure to hold per chip specific memory address + * information for nest pmus. Nest Counter data are exported + * in per-chip reserved memory region by the PORE Engine. + */ +struct perchip_nest_info { + u32 chip_id; + u64 pbase; + u64 vbase[IMC_NEST_MAX_PAGES]; + u64 size; +}; + +/* + * Place holder for nest pmu events and values. + */ +struct imc_events { + char *ev_name; + char *ev_value; +}; + +/* + * Device tree parser code detects IMC pmu support and + * registers new IMC pmus. This structure will + * hold the pmu functions and attrs for each imc pmu and + * will be referenced at the time of pmu registration. + */ +struct imc_pmu { + struct pmu pmu; + int domain; + const struct attribute_group *attr_groups[4]; +}; + +/* + * Domains for IMC PMUs + */ +#define IMC_DOMAIN_NEST 1 +#define IMC_DOMAIN_UNKNOWN -1 + +#endif /* PPC_POWERNV_IMC_PMU_DEF_H */