From patchwork Mon Apr 3 11:19:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aniruddha Banerjee X-Patchwork-Id: 746405 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vxV5W2LCNz9s7r for ; Mon, 3 Apr 2017 21:20:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752870AbdDCLUM convert rfc822-to-8bit (ORCPT ); Mon, 3 Apr 2017 07:20:12 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13317 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752172AbdDCLUH (ORCPT ); Mon, 3 Apr 2017 07:20:07 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 03 Apr 2017 04:20:10 -0700 Received: from HQMAIL106.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 03 Apr 2017 04:20:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 03 Apr 2017 04:20:02 -0700 Received: from DRUKMAIL101.nvidia.com (10.25.59.19) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Mon, 3 Apr 2017 11:20:00 +0000 Received: from BGMAIL102.nvidia.com (10.25.59.11) by drukmail101.nvidia.com (10.25.59.19) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Mon, 3 Apr 2017 11:19:55 +0000 Received: from BGMAIL102.nvidia.com ([::1]) by bgmail102.nvidia.com ([fe80::98ed:9144:9547:b95b%20]) with mapi id 15.00.1263.000; Mon, 3 Apr 2017 11:19:55 +0000 From: Aniruddha Banerjee To: Thierry Reding , Jonathan Hunter CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , Alexander Van Brunt Subject: [PATCH 1/1] arm64: tegra: fix PPI interrupt flag Thread-Topic: [PATCH 1/1] arm64: tegra: fix PPI interrupt flag Thread-Index: AdKsbA1WgcTM5DT8Tj+3MfWorHmkVA== Date: Mon, 3 Apr 2017 11:19:54 +0000 Message-ID: <7fad40fbcaa94c1ea46328e78b46443b@bgmail102.nvidia.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.24.52.227] MIME-Version: 1.0 Content-Language: en-US Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The interrupt flag for PPI should not be set to any value, since the register is read-only. Fix the flags for the PPI interrupts to IRQ_TYPE_NONE, so that there is no write to the read-only register. Signed-off-by: Aniruddha Banerjee --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 8 ++++---- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 ++++---- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 3f3a46a4bd01..219fb3c6a273 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -1093,13 +1093,13 @@ timer { compatible = "arm,armv7-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>; interrupt-parent = <&gic>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 62fa85ae0271..e602299f7694 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -390,13 +390,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>; interrupt-parent = <&gic>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2f832df29da8..6f3060b40a40 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1214,13 +1214,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_NONE)>; interrupt-parent = <&gic>; };