From patchwork Mon Apr 3 07:41:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: maddy X-Patchwork-Id: 746291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vxPGV2M7Jz9s7r for ; Mon, 3 Apr 2017 17:42:58 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vxPGV1YVYzDqJt for ; Mon, 3 Apr 2017 17:42:58 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vxPFq2H5fzDq7Z for ; Mon, 3 Apr 2017 17:42:23 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v337YMJx004328 for ; Mon, 3 Apr 2017 03:42:16 -0400 Received: from e28smtp03.in.ibm.com (e28smtp03.in.ibm.com [125.16.236.3]) by mx0b-001b2d01.pphosted.com with ESMTP id 29j961d0wc-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 03 Apr 2017 03:42:16 -0400 Received: from localhost by e28smtp03.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 3 Apr 2017 13:12:09 +0530 Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay03.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v337g9eS19595264 for ; Mon, 3 Apr 2017 13:12:09 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v337g74Q009608 for ; Mon, 3 Apr 2017 13:12:08 +0530 Received: from SrihariSrinidhi.in.ibm.com ([9.79.210.235]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v337fxlu009412; Mon, 3 Apr 2017 13:12:06 +0530 From: Madhavan Srinivasan To: stewart@linux.vnet.ibm.com Date: Mon, 3 Apr 2017 13:11:41 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491205307-20408-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1491205307-20408-1-git-send-email-maddy@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17040307-0008-0000-0000-0000054D6BBE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17040307-0009-0000-0000-00001358C87F Message-Id: <1491205307-20408-5-git-send-email-maddy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-03_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704030070 Subject: [Skiboot] [PATCH v8 04/10] skiboot: Nest IMC macro definitions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Hemant Kumar Add the macros needed for Nest IMC (In Memory Collection) instrumentation support by creating a new file in include/ called "imc.h". Also, add a header "nest_imc.h" containing an array of possible list of nest PMUs. These macros are needed to discover the catalog subpartition, enable and disable the nest IMC instrumentation. Signed-off-by: Hemant Kumar Reviewed-by: Oliver O'Halloran [maddy: Removed nest_imc.h and updated few macros] Signed-off-by: Madhavan Srinivasan Signed-off-by: Madhavan Srinivasan --- include/imc.h | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 include/imc.h diff --git a/include/imc.h b/include/imc.h new file mode 100644 index 000000000000..3e3205431981 --- /dev/null +++ b/include/imc.h @@ -0,0 +1,118 @@ +/* Copyright 2016 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * IMC (In-Memory Collection) : + * Power9 has IMC instrumentation support with which several metrics of the + * platform can be monitored. These metrics are backed by the + * Performance Monitoring Units (PMUs) and their counters. + * IMC counters run continuously from startup to shutdown and hence, the + * name and data from these counters are fed directly into a pre-defined + * memory location. + * + * Depending on the counters' location and monitoring engines, they are + * classified into three domains : + * Nest IMC, core IMC and thread IMC. + * + * Nest Counters : + * Nest counters are per-chip counters and can help in providing utilisation + * metrics like memory bandwidth, Xlink/Alink bandwidth etc. + * A microcode in OCC programs the nest counters and moves counter values to + * per chip HOMER region in a fixed offset for each unit. Engine has a + * control block structure for communication with Hypervisor(Host OS). + */ + +#ifndef __IMC_H +#define __IMC_H + +/* + * Control Block structure offset in HOMER nest Region + */ +#define P9_CB_STRUCT_OFFSET 0x1BFC00 +#define P9_CB_STRUCT_CMD 0x1BFC08 +#define P9_CB_STRUCT_SPEED 0x1BFC10 + +/* Nest microcode Status */ +#define NEST_IMC_PAUSE 0x2 +#define NEST_IMC_RESUME 0x1 +#define NEST_IMC_NOP 0 + +/* + * Control Block Structure: + * + * Name Producer Consumer Values Desc + * IMCRunStatus IMC Code Hypervisor 0 Initializing + * (Host OS) 1 Running + * 2 Paused + * + * IMCCommand Hypervisor IMC Code 0 NOP + * 1 Resume + * 2 Pause + * 3 Clear and Restart + * + * IMCCollection Hypervisor IMC Code 0 128us + * Speed 1 256us + * 2 1ms + * 3 4ms + * 4 16ms + * 5 64ms + * 6 256ms + * 7 1000ms + * + * IMCAvailability IMC Code Hypervisor - 64-bit value describes + * the Vector Nest PMU + * availability. + * Bits 0-47 denote the + * availability of 48 different + * nest units. + * Rest are reserved. For details + * regarding which bit belongs + * to which unit, see + * include/nest_imc.h. + * If a bit is unset (0), + * then, the corresponding unit + * is unavailable. If its set (1), + * then, the unit is available. + * + * IMCRun Mode Hypervisor IMC Code 0 Normal Mode (Monitor Mode) + * 1 Debug Mode 1 (PB) + * 2 Debug Mode 2 (MEM) + * 3 Debug Mode 3 (PCIE) + * 4 Debug Mode 4 (CAPP) + * 5 Debug Mode 5 (NPU 1) + * 6 Debug Mode 6 (NPU 2) + */ +struct imc_chip_cb +{ + u64 imc_chip_run_status; + u64 imc_chip_command; + u64 imc_chip_collection_speed; + u64 imc_chip_avl_vector; + u64 imc_chip_run_mode; +}; + +/* Size of IMC dtb LID (256KBytes) */ +#define IMC_DTB_SIZE 0x40000 + +/* + * Nest IMC operations + */ +#define NEST_IMC_ENABLE 0x1 +#define NEST_IMC_DISABLE 0x2 + +#define MAX_AVL 48 + +#endif /* __IMC_H */