From patchwork Sat Apr 1 07:18:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haren Myneni X-Patchwork-Id: 745899 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vw8qh0S5Rz9s7C for ; Sat, 1 Apr 2017 18:18:56 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vw8qg6mmqzDqJC for ; Sat, 1 Apr 2017 18:18:55 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vw8qZ0nNDzDqC4 for ; Sat, 1 Apr 2017 18:18:49 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v317E1ea070553 for ; Sat, 1 Apr 2017 03:18:37 -0400 Received: from e12.ny.us.ibm.com (e12.ny.us.ibm.com [129.33.205.202]) by mx0a-001b2d01.pphosted.com with ESMTP id 29j6hc1t2e-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sat, 01 Apr 2017 03:18:37 -0400 Received: from localhost by e12.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sat, 1 Apr 2017 03:18:34 -0400 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v317INL654067344; Sat, 1 Apr 2017 07:18:23 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F2CF4AC058; Sat, 1 Apr 2017 03:18:13 -0400 (EDT) Received: from [9.70.82.143] (unknown [9.70.82.143]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id 32EE8AC03F; Sat, 1 Apr 2017 03:18:13 -0400 (EDT) From: Haren Myneni To: stewart@linux.vnet.ibm.com Date: Sat, 01 Apr 2017 00:18:20 -0700 Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 X-TM-AS-GCONF: 00 x-cbid: 17040107-0048-0000-0000-0000014624A5 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006875; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000207; SDB=6.00841534; UDB=6.00414369; IPR=6.00619626; BA=6.00005251; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014874; XFM=3.00000013; UTC=2017-04-01 07:18:35 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17040107-0049-0000-0000-00004025E964 Message-Id: <1491031100.29552.13.camel@hbabu-laptop> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-01_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704010071 Subject: [Skiboot] [PATCH V3 4/5] NX: Add P9 NX support for gzip compression engine X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hbabu@us.ibm.com, apopple@au1.ibm.com, skiboot@lists.ozlabs.org, michael.neuling@au1.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" [PATCH V3 4/5] NX: Add P9 NX support for gzip compression engine Power 9 introduces NX gzip compression engine. This patch adds gzip compression support in NX. Virtual Accelerator Switch (VAS) is used to access NX gzip engine and the channel configuration will be done with the receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used to configure RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot configures User Mode Access Control (UMAC) noitify match register with these values and also enables other registers to enable / disable the engine. Creates the following device-tree entries to provide RxFIFO address, lpid, pid and tid values so that kernel can drive P9 NX gzip engine. The following nodes are located under an xscom node: /xscom@/nx@ /ibm,nx-gzip-high : High priority gzip RxFIFO /ibm,nx-gzip-normal : Normal priority gzip RxFIFO Each RxFIFO node contains: rx-fifo-address : RxFIFO address lpid : 0xfff (1's for 12 bits in UMAC notify match regsiter) pid : gzip coprocessor type tid : counter for gzip Signed-off-by: Haren Myneni --- hw/Makefile.inc | 2 +- hw/nx-compress.c | 1 + hw/nx-gzip.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/nx.h | 1 + 4 files changed, 130 insertions(+), 1 deletions(-) create mode 100644 hw/nx-gzip.c diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 97c909e..d4c4fcc 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -2,7 +2,7 @@ SUBDIRS += hw HW_OBJS = xscom.o chiptod.o gx.o cec.o lpc.o lpc-uart.o psi.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o -HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o +HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o diff --git a/hw/nx-compress.c b/hw/nx-compress.c index 9970d55..674fd4a 100644 --- a/hw/nx-compress.c +++ b/hw/nx-compress.c @@ -217,6 +217,7 @@ void nx_create_compress_node(struct dt_node *node) return; p9_nx_enable_842(node, gcid, pb_base); + p9_nx_enable_gzip(node, gcid, pb_base); } else nx_enable_842(node, gcid, pb_base); } diff --git a/hw/nx-gzip.c b/hw/nx-gzip.c new file mode 100644 index 0000000..8b384f1 --- /dev/null +++ b/hw/nx-gzip.c @@ -0,0 +1,127 @@ +/* Copyright 2016 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include + +#define EE (1) /* enable gzip engine */ + +static int nx_cfg_gzip_umac(struct dt_node *node, u32 gcid, u32 pb_base) +{ + int rc; + u64 umac_bar, umac_ctrl, umac_notify; + struct dt_node *nx_node; + static u32 nxgzip_tid = 1; /* tid counter within coprocessor type */ + + nx_node = dt_new(node, "ibm,nx-gzip-high"); + umac_bar = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_BAR; + umac_ctrl = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL; + umac_notify = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_NOTIFY_MATCH; + + rc = nx_cfg_rx_fifo(nx_node, gcid, umac_bar, umac_notify, umac_ctrl, + NX_CT_GZIP, nxgzip_tid++); + if (rc) + return rc; + + nx_node = dt_new(node, "ibm,nx-gzip-normal"); + umac_bar = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_BAR; + umac_ctrl = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL; + umac_notify = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH; + + rc = nx_cfg_rx_fifo(nx_node, gcid, umac_bar, umac_notify, umac_ctrl, + NX_CT_GZIP, nxgzip_tid++); + + return rc; +} + +static int nx_cfg_gzip_dma(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_PREFETCH, cfg, + DMA_COMPRESS_PREFETCH); + cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_PREFETCH, cfg, + DMA_DECOMPRESS_PREFETCH); + + cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_MAX_RR, cfg, + DMA_COMPRESS_MAX_RR); + cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_MAX_RR, cfg, + DMA_DECOMPRESS_MAX_RR); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid, + (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_gzip_ee(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P9_EE_CFG_CH4, cfg, EE); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +void p9_nx_enable_gzip(struct dt_node *node, u32 gcid, u32 pb_base) +{ + u64 cfg_dma, cfg_ee; + int rc; + + prlog(PR_INFO, "NX%d: gzip at 0x%x\n", gcid, pb_base); + + cfg_dma = pb_base + NX_P9_DMA_CFG; + cfg_ee = pb_base + NX_P9_EE_CFG; + + rc = nx_cfg_gzip_dma(gcid, cfg_dma); + if (rc) + return; + + rc = nx_cfg_gzip_ee(gcid, cfg_ee); + if (rc) + return; + + rc = nx_cfg_gzip_umac(node, gcid, pb_base); + if (rc) + return; + + prlog(PR_INFO, "NX%d: gzip Coprocessor Enabled\n", gcid); +} diff --git a/include/nx.h b/include/nx.h index ada5157..8582b2f 100644 --- a/include/nx.h +++ b/include/nx.h @@ -405,6 +405,7 @@ extern void nx_create_compress_node(struct dt_node *); extern void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base); extern void p9_nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base); +extern void p9_nx_enable_gzip(struct dt_node *node, u32 gcid, u32 pb_base); extern int nx_cfg_rx_fifo(struct dt_node *node, u32 gcid, u64 umac_bar, u64 umac_notify, u64 umac_ctrl, u32 pid,