[V3,2/5] NX: Organize NX compression code to include 842 and gzip engines support

Submitted by Haren Myneni on April 1, 2017, 7:16 a.m.

Details

Message ID 1491031009.29552.11.camel@hbabu-laptop
State New
Headers show

Commit Message

Haren Myneni April 1, 2017, 7:16 a.m.
[PATCH V3 2/5] NX: Organize NX compression code to include 842 and gzip engines support

P9 NX also supports gzip compression. So this patch creates
nx-compress.c and reorg nx-842.c code so that common functions that are
needed for both 842 and gzip compression will be moved in to
nx-compress.c. This patch does not change the actual functionality.

Signed-off-by: Haren Myneni <haren@us.ibm.com>
---
 hw/Makefile.inc  |    2 +-
 hw/nx-842.c      |   26 +++++++-------------------
 hw/nx-compress.c |   34 ++++++++++++++++++++++++++++++++++
 hw/nx.c          |    2 +-
 include/nx.h     |   18 +++++++++++++++---
 5 files changed, 58 insertions(+), 24 deletions(-)
 create mode 100644 hw/nx-compress.c

Patch hide | download patch | download mbox

diff --git a/hw/Makefile.inc b/hw/Makefile.inc
index f2dc328..97c909e 100644
--- a/hw/Makefile.inc
+++ b/hw/Makefile.inc
@@ -2,7 +2,7 @@ 
 SUBDIRS += hw
 HW_OBJS  = xscom.o chiptod.o gx.o cec.o lpc.o lpc-uart.o psi.o
 HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o
-HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-842.o
+HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o
 HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o
 HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o
 HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o
diff --git a/hw/nx-842.c b/hw/nx-842.c
index f462f7a..031de03 100644
--- a/hw/nx-842.c
+++ b/hw/nx-842.c
@@ -24,11 +24,6 @@ 
 /* Configuration settings */
 #define CFG_842_FC_ENABLE	(0x1f) /* enable all 842 functions */
 #define CFG_842_ENABLE		(1) /* enable 842 engines */
-#define DMA_COMPRESS_PREFETCH	(1) /* enable prefetching (on P8) */
-#define DMA_DECOMPRESS_PREFETCH	(1) /* enable prefetching (on P8) */
-#define DMA_COMPRESS_MAX_RR	(15) /* range 1-15 */
-#define DMA_DECOMPRESS_MAX_RR	(15) /* range 1-15 */
-#define DMA_SPBC		(1) /* write SPBC in CPB */
 #define DMA_CSB_WR		NX_DMA_CSB_WR_CI
 #define DMA_COMPLETION_MODE	NX_DMA_COMPLETION_MODE_CI
 #define DMA_CPB_WR		NX_DMA_CPB_WR_CI_PAD
@@ -90,7 +85,7 @@  static int nx_cfg_842(u32 gcid, u64 xcfg)
 	return rc;
 }
 
-static int nx_cfg_dma(u32 gcid, u64 xcfg)
+static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
 {
 	u64 cfg;
 	int rc;
@@ -100,9 +95,9 @@  static int nx_cfg_dma(u32 gcid, u64 xcfg)
 		return rc;
 
 	if (proc_gen == proc_gen_p8) {
-		cfg = SETFIELD(NX_P8_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
+		cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
 			       DMA_COMPRESS_PREFETCH);
-		cfg = SETFIELD(NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
+		cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
 			       DMA_DECOMPRESS_PREFETCH);
 	}
 
@@ -131,7 +126,7 @@  static int nx_cfg_dma(u32 gcid, u64 xcfg)
 	return rc;
 }
 
-static int nx_cfg_ee(u32 gcid, u64 xcfg)
+static int nx_cfg_842_ee(u32 gcid, u64 xcfg)
 {
 	u64 cfg;
 	int rc;
@@ -153,18 +148,11 @@  static int nx_cfg_ee(u32 gcid, u64 xcfg)
 	return rc;
 }
 
-void nx_create_842_node(struct dt_node *node)
+void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
 {
-	u32 gcid;
-	u32 pb_base;
 	u64 cfg_dma, cfg_842, cfg_ee;
 	int rc;
 
-	gcid = dt_get_chip_id(node);
-	pb_base = dt_get_address(node, 0, NULL);
-
-	prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base);
-
 	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
 		cfg_dma = pb_base + NX_P7_DMA_CFG;
 		cfg_842 = pb_base + NX_P7_842_CFG;
@@ -178,7 +166,7 @@  void nx_create_842_node(struct dt_node *node)
 		return;
 	}
 
-	rc = nx_cfg_dma(gcid, cfg_dma);
+	rc = nx_cfg_842_dma(gcid, cfg_dma);
 	if (rc)
 		return;
 
@@ -186,7 +174,7 @@  void nx_create_842_node(struct dt_node *node)
 	if (rc)
 		return;
 
-	rc = nx_cfg_ee(gcid, cfg_ee);
+	rc = nx_cfg_842_ee(gcid, cfg_ee);
 	if (rc)
 		return;
 
diff --git a/hw/nx-compress.c b/hw/nx-compress.c
new file mode 100644
index 0000000..2ea2734
--- /dev/null
+++ b/hw/nx-compress.c
@@ -0,0 +1,34 @@ 
+/* Copyright 2015 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * 	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <skiboot.h>
+#include <chip.h>
+#include <xscom.h>
+#include <io.h>
+#include <cpu.h>
+#include <nx.h>
+
+void nx_create_compress_node(struct dt_node *node)
+{
+	u32 gcid, pb_base;
+
+	gcid = dt_get_chip_id(node);
+	pb_base = dt_get_address(node, 0, NULL);
+
+	prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base);
+
+	nx_enable_842(node, gcid, pb_base);
+}
diff --git a/hw/nx.c b/hw/nx.c
index 83528d1..020c9e4 100644
--- a/hw/nx.c
+++ b/hw/nx.c
@@ -29,6 +29,6 @@  void nx_init(void)
 	dt_for_each_compatible(dt_root, node, "ibm,power-nx") {
 		nx_create_rng_node(node);
 		nx_create_crypto_node(node);
-		nx_create_842_node(node);
+		nx_create_compress_node(node);
 	}
 }
diff --git a/include/nx.h b/include/nx.h
index 0ba1432..f2eb07a 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -75,13 +75,13 @@ 
 /* DMA */
 #define NX_P7_DMA_CFG		NX_P7_SAT(0x1, 0x02)
 #define NX_P8_DMA_CFG		NX_P8_SAT(0x1, 0x02)
-#define   NX_P8_DMA_CFG_842_COMPRESS_PREFETCH	PPC_BIT(23)
-#define   NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH	PPC_BIT(24)
 #define NX_P9_DMA_CFG		NX_P9_SAT(0x1, 0x02)
 #define   NX_DMA_CFG_GZIP_COMPRESS_MAX_RR	PPC_BITMASK(8, 11)
 #define   NX_DMA_CFG_GZIP_DECOMPRESS_MAX_RR	PPC_BITMASK(12, 15)
 #define   NX_DMA_CFG_GZIP_COMPRESS_PREFETCH	PPC_BIT(16)
 #define   NX_DMA_CFG_GZIP_DECOMPRESS_PREFETCH	PPC_BIT(17)
+#define   NX_DMA_CFG_842_COMPRESS_PREFETCH	PPC_BIT(23)
+#define   NX_DMA_CFG_842_DECOMPRESS_PREFETCH	PPC_BIT(24)
 #define   NX_DMA_CFG_AES_SHA_MAX_RR		PPC_BITMASK(25, 28)
 #define   NX_DMA_CFG_AMF_MAX_RR			PPC_BITMASK(29, 32)
 #define   NX_DMA_CFG_842_COMPRESS_MAX_RR	PPC_BITMASK(33, 36)
@@ -385,13 +385,25 @@ 
 #define NX_DMA_OUTPUT_DATA_WR_CI	(1)
 
 
+/*
+ * NX compression configuration settings for 842 (on p8 and later)
+ * and gzip (p9 and later) engines
+ */
+#define DMA_COMPRESS_PREFETCH	(1) /* enable prefetching */
+#define DMA_DECOMPRESS_PREFETCH	(1) /* enable prefetching */
+#define DMA_COMPRESS_MAX_RR	(15) /* range 1-15 */
+#define DMA_DECOMPRESS_MAX_RR	(15) /* range 1-15 */
+#define DMA_SPBC		(1) /* write SPBC in CPB */
+
 /******************************/
 /* NX node creation functions */
 /******************************/
 
 extern void nx_create_rng_node(struct dt_node *);
 extern void nx_create_crypto_node(struct dt_node *);
-extern void nx_create_842_node(struct dt_node *);
+extern void nx_create_compress_node(struct dt_node *);
+
+extern void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base);
 
 extern void nx_init(void);