[V2,1/5] capi: Externalize capp timebase synchronization

Submitted by Christophe Lombard on March 31, 2017, 4:52 p.m.

Details

Message ID 1490979160-14535-2-git-send-email-clombard@linux.vnet.ibm.com
State Under Review
Headers show

Commit Message

Christophe Lombard March 31, 2017, 4:52 p.m.
Externalize the chiptod code. this code will be common for PHB3 and
PHB4.
The reference to the structure PHB3 is remove and new arguments appear
due to specific address registers.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
---
 hw/chiptod.c      | 40 ++++++++++++++++++----------------------
 hw/phb3.c         |  2 +-
 include/chiptod.h |  4 ++--
 3 files changed, 21 insertions(+), 25 deletions(-)

Comments

Andrew Donnellan April 3, 2017, 1:47 a.m.
On 01/04/17 03:52, Christophe Lombard wrote:
> Externalize the chiptod code. this code will be common for PHB3 and
> PHB4.
> The reference to the structure PHB3 is remove and new arguments appear
> due to specific address registers.
>
> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>

Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>

Patch hide | download patch | download mbox

diff --git a/hw/chiptod.c b/hw/chiptod.c
index 16dd0ae..746876a 100644
--- a/hw/chiptod.c
+++ b/hw/chiptod.c
@@ -21,10 +21,8 @@ 
 #include <skiboot.h>
 #include <xscom.h>
 #include <pci.h>
-#include <phb3.h>
 #include <chiptod.h>
 #include <chip.h>
-#include <capp.h>
 #include <io.h>
 #include <cpu.h>
 #include <timebase.h>
@@ -1792,7 +1790,7 @@  void chiptod_init(void)
 
 /* CAPP timebase sync */
 
-static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)
+static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset)
 {
 	uint64_t tfmr;
 	unsigned long timeout = 0;
@@ -1808,12 +1806,12 @@  static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)
 	tfmr |= SPR_TFMR_TFMR_CORRUPT;
 
 	/* Write CAPP TFMR */
-	xscom_write(chip_id, CAPP_TFMR + offset, tfmr);
+	xscom_write(chip_id, tfmr_addr + offset, tfmr);
 
 	/* We have to write "Clear TB Errors" again */
 	tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
 	/* Write CAPP TFMR */
-	xscom_write(chip_id, CAPP_TFMR + offset, tfmr);
+	xscom_write(chip_id, tfmr_addr + offset, tfmr);
 
 	do {
 		if (++timeout >= TIMEOUT_LOOPS) {
@@ -1821,7 +1819,7 @@  static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)
 			return false;
 		}
 		/* Read CAPP TFMR */
-		xscom_read(chip_id, CAPP_TFMR + offset, &tfmr);
+		xscom_read(chip_id, tfmr_addr + offset, &tfmr);
 		if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
 			prerror("CAPP: TB error reset: corrupt TFMR!\n");
 			return false;
@@ -1830,20 +1828,20 @@  static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)
 	return true;
 }
 
-static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t offset)
+static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset)
 {
 	uint64_t timeout = 0;
 	uint64_t tfmr;
 
 	/* Switch CAPP timebase to "Not Set" state */
 	tfmr = base_tfmr | SPR_TFMR_LOAD_TOD_MOD;
-	xscom_write(chip_id, CAPP_TFMR + offset, tfmr);
+	xscom_write(chip_id, tfmr_addr + offset, tfmr);
 	do {
 		if (++timeout >= (TIMEOUT_LOOPS*2)) {
 			prerror("CAPP: TB \"Not Set\" timeout\n");
 			return false;
 		}
-		xscom_read(chip_id, CAPP_TFMR + offset, &tfmr);
+		xscom_read(chip_id, tfmr_addr + offset, &tfmr);
 		if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
 			prerror("CAPP: TB \"Not Set\" TFMR corrupt\n");
 			return false;
@@ -1878,7 +1876,7 @@  static bool chiptod_wait_for_chip_sync(void)
 	return true;
 }
 
-static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset)
+static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset)
 {
 	uint64_t tfmr;
 	uint64_t timeout = 0;
@@ -1889,7 +1887,7 @@  static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset)
 			prerror("CAPP: TB Invalid!\n");
 			return false;
 		}
-		xscom_read(chip_id, CAPP_TFMR + offset, &tfmr);
+		xscom_read(chip_id, tfmr_addr + offset, &tfmr);
 		if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
 			prerror("CAPP: TFMR corrupt!\n");
 			return false;
@@ -1898,25 +1896,23 @@  static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset)
 	return true;
 }
 
-bool chiptod_capp_timebase_sync(struct phb3 *p)
+bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,
+				uint32_t tb_addr, uint32_t offset)
 {
 	uint64_t tfmr;
 	uint64_t capp_tb;
 	int64_t delta;
-	uint32_t offset;
 	unsigned int retry = 0;
 
-	offset = PHB3_CAPP_REG_OFFSET(p);
-
 	/* Set CAPP TFMR to base tfmr value */
-	xscom_write(p->chip_id, CAPP_TFMR + offset, base_tfmr);
+	xscom_write(chip_id, tfmr_addr + offset, base_tfmr);
 
 	/* Reset CAPP TB errors before attempting the sync */
-	if (!chiptod_capp_reset_tb_errors(p->chip_id, offset))
+	if (!chiptod_capp_reset_tb_errors(chip_id, tfmr_addr, offset))
 		return false;
 
 	/* Switch CAPP TB to "Not Set" state */
-	if (!chiptod_capp_mod_tb(p->chip_id, offset))
+	if (!chiptod_capp_mod_tb(chip_id, tfmr_addr, offset))
 		return false;
 
 	/* Sync CAPP TB with core TB, retry while difference > 16usecs */
@@ -1928,19 +1924,19 @@  bool chiptod_capp_timebase_sync(struct phb3 *p)
 
 		/* Make CAPP ready to get the TB, wait for chip sync */
 		tfmr = base_tfmr | SPR_TFMR_MOVE_CHIP_TOD_TO_TB;
-		xscom_write(p->chip_id, CAPP_TFMR + offset, tfmr);
+		xscom_write(chip_id, tfmr_addr + offset, tfmr);
 		if (!chiptod_wait_for_chip_sync())
 			return false;
 
 		/* Set CAPP TB from core TB */
-		xscom_write(p->chip_id, CAPP_TB + offset, mftb());
+		xscom_write(chip_id, tb_addr + offset, mftb());
 
 		/* Wait for CAPP TFMR tb_valid bit */
-		if (!chiptod_capp_check_tb_running(p->chip_id, offset))
+		if (!chiptod_capp_check_tb_running(chip_id, tfmr_addr, offset))
 			return false;
 
 		/* Read CAPP TB, read core TB, compare */
-		xscom_read(p->chip_id, CAPP_TB + offset, &capp_tb);
+		xscom_read(chip_id, tb_addr + offset, &capp_tb);
 		delta = mftb() - capp_tb;
 		if (delta < 0)
 			delta = -delta;
diff --git a/hw/phb3.c b/hw/phb3.c
index 9bc9d78..05466c2 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -3724,7 +3724,7 @@  static int64_t enable_capi_mode(struct phb3 *p, uint64_t pe_number, bool dma_mod
 
 	phb3_init_capp_regs(p, dma_mode);
 
-	if (!chiptod_capp_timebase_sync(p)) {
+	if (!chiptod_capp_timebase_sync(p->chip_id, CAPP_TFMR, CAPP_TB, PHB3_CAPP_REG_OFFSET(p))) {
 		PHBERR(p, "CAPP: Failed to sync timebase\n");
 		return OPAL_HARDWARE;
 	}
diff --git a/include/chiptod.h b/include/chiptod.h
index 64df8bc..fd5cd96 100644
--- a/include/chiptod.h
+++ b/include/chiptod.h
@@ -32,7 +32,7 @@  extern bool chiptod_wakeup_resync(void);
 extern int chiptod_recover_tb_errors(void);
 extern void chiptod_reset_tb(void);
 extern bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable);
-struct phb3;
-extern bool chiptod_capp_timebase_sync(struct phb3 *p);
+extern bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,
+				       uint32_t tb_addr, uint32_t offset);
 
 #endif /* __CHIPTOD_H */