From patchwork Thu Mar 30 19:42:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 745397 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vvFWX6MRDz9s0g for ; Fri, 31 Mar 2017 06:46:48 +1100 (AEDT) Received: from localhost ([::1]:37418 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ctg1u-00069f-DB for incoming@patchwork.ozlabs.org; Thu, 30 Mar 2017 15:46:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ctfy9-0003Ov-FQ for qemu-devel@nongnu.org; Thu, 30 Mar 2017 15:42:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ctfy8-0007IQ-7j for qemu-devel@nongnu.org; Thu, 30 Mar 2017 15:42:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46160) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ctfy3-0007G2-A2; Thu, 30 Mar 2017 15:42:47 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 363E3C0092C9; Thu, 30 Mar 2017 19:42:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 363E3C0092C9 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=eric.auger@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 363E3C0092C9 Received: from localhost.localdomain.com (ovpn-117-27.ams2.redhat.com [10.36.117.27]) by smtp.corp.redhat.com (Postfix) with ESMTP id E6F5777D53; Thu, 30 Mar 2017 19:42:40 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, edgar.iglesias@gmail.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, prem.mallappa@gmail.com Date: Thu, 30 Mar 2017 21:42:17 +0200 Message-Id: <1490902938-9009-5-git-send-email-eric.auger@redhat.com> In-Reply-To: <1490902938-9009-1-git-send-email-eric.auger@redhat.com> References: <1490902938-9009-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 30 Mar 2017 19:42:46 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC v3 4/5] hw/arm/virt: Add SMMUv3 to the virt board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Radha.Chintakuntla@cavium.com, christoffer.dall@linaro.org, Sunil.Goutham@cavium.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Prem Mallappa Add code to instantiate an smmu-v3 in mach-virt. A new boolean flag is introduced in VirtMachineState to allow this instantiation. It is currently false. Signed-off-by: Prem Mallappa Signed-off-by: Eric Auger --- v2 -> v3: - vbi was removed. Use vms instead - migrate to new smmu binding format (iommu-map) - don't use appendprop anymore - add vms->smmu and guard instantiation with this latter - interrupts type changed to edge --- hw/arm/virt.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 4 ++++ 2 files changed, 62 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5f62a03..c00efb2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -56,6 +56,7 @@ #include "hw/smbios/smbios.h" #include "qapi/visitor.h" #include "standard-headers/linux/input.h" +#include "hw/arm/smmuv3.h" #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -139,6 +140,7 @@ static const MemMapEntry a15memmap[] = { [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, + [VIRT_SMMU] = { 0x09050000, 0x00020000 }, /* 128K, needed */ [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -159,6 +161,7 @@ static const int a15irqmap[] = { [VIRT_SECURE_UART] = 8, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ + [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; @@ -969,6 +972,52 @@ static void create_pcie_irq_map(const VirtMachineState *vms, 0x7 /* PCI irq */); } +static void alloc_smmu_phandle(VirtMachineState *vms) +{ + if (vms->smmu && !vms->smmu_phandle) { + vms->smmu_phandle = qemu_fdt_alloc_phandle(vms->fdt); + } +} + +static void create_smmu(const VirtMachineState *vms, qemu_irq *pic) +{ + char *smmu; + const char compat[] = "arm,smmu-v3"; + int irq = vms->irqmap[VIRT_SMMU]; + hwaddr base = vms->memmap[VIRT_SMMU].base; + hwaddr size = vms->memmap[VIRT_SMMU].size; + const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; + + if (!vms->smmu) { + return; + } + + sysbus_create_varargs("smmuv3", base, pic[irq], pic[irq + 1], + pic[irq + 2], pic[irq + 3], NULL); + + smmu = g_strdup_printf("/smmuv3@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, smmu); + qemu_fdt_setprop(vms->fdt, smmu, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(vms->fdt, smmu, "reg", 2, base, 2, size); + + qemu_fdt_setprop_cells(vms->fdt, smmu, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(vms->fdt, smmu, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop_cell(vms->fdt, smmu, "clocks", vms->clock_phandle); + qemu_fdt_setprop_string(vms->fdt, smmu, "clock-names", "apb_pclk"); + + qemu_fdt_setprop_cell(vms->fdt, smmu, "#iommu-cells", 1); + + qemu_fdt_setprop_cell(vms->fdt, smmu, "phandle", vms->smmu_phandle); + g_free(smmu); +} + static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) { hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; @@ -1081,6 +1130,11 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); + if (vms->smmu) { + qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", + 0x0, vms->smmu_phandle, 0x0, 0x10000); + } + g_free(nodename); } @@ -1402,8 +1456,12 @@ static void machvirt_init(MachineState *machine) create_rtc(vms, pic); + alloc_smmu_phandle(vms); + create_pcie(vms, pic); + create_smmu(vms, pic); + create_gpio(vms, pic); /* Create mmio transports, so the user can create virtio backends diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 33b0ff3..164a531 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -38,6 +38,7 @@ #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 +#define NUM_SMMU_IRQS 4 #define ARCH_GICV3_MAINT_IRQ 9 @@ -59,6 +60,7 @@ enum { VIRT_GIC_V2M, VIRT_GIC_ITS, VIRT_GIC_REDIST, + VIRT_SMMU, VIRT_UART, VIRT_MMIO, VIRT_RTC, @@ -95,6 +97,7 @@ typedef struct { bool highmem; bool its; bool virt; + bool smmu; int32_t gic_version; struct arm_boot_info bootinfo; const MemMapEntry *memmap; @@ -105,6 +108,7 @@ typedef struct { uint32_t clock_phandle; uint32_t gic_phandle; uint32_t msi_phandle; + uint32_t smmu_phandle; int psci_conduit; } VirtMachineState;