Patchwork [U-Boot,v4,1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs

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Submitter Prafulla Wadaskar
Date Dec. 7, 2010, 5:06 p.m.
Message ID <1291741587-12484-1-git-send-email-prafulla@marvell.com>
Download mbox | patch
Permalink /patch/74531/
State Accepted
Commit 6c08d5dcf845c798173b883d7cc3d453de1dbd7e
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Comments

Prafulla Wadaskar - Dec. 7, 2010, 5:06 p.m.
ARMADA 100 Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref: http://www.marvell.com/products/processors/applications/armada_100

SoC versions Supported:
1) ARMADA168/88AP168	(Aspen P)
2) ARMADA166/88AP166	(Aspen M)
3) ARMADA162/88AP162	(Aspen L)

Contributors:
Eric Miao <eric.y.miao@marvell.com>
Lei Wen <leiwen@marvell.com>
Mahavir Jain <mjain@marvell.com>

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log V2:
1. C-struct used for dram.c
2. lib declaration changed from .a to .o
3. Implemented review feedback for v1

Changelog V3:
1. timer variables in gt_t used insted of locally defined global variables
2. register global pointer moved to respective functions
3. Macro READ_TIMER converted to function read_timer()
4. c-struc in armada100.h fixed for wrong padding

Changelog V4:
1. timer.c updated for build warning

 arch/arm/cpu/arm926ejs/armada100/Makefile       |   46 +++++
 arch/arm/cpu/arm926ejs/armada100/cpu.c          |   92 ++++++++++
 arch/arm/cpu/arm926ejs/armada100/dram.c         |  131 ++++++++++++++
 arch/arm/cpu/arm926ejs/armada100/timer.c        |  207 +++++++++++++++++++++++
 arch/arm/include/asm/arch-armada100/armada100.h |  121 +++++++++++++
 arch/arm/include/asm/arch-armada100/cpu.h       |   53 ++++++
 6 files changed, 650 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
 create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
 create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
Eric Miao - Dec. 8, 2010, 2:32 a.m.
On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com> wrote:
> ARMADA 100 Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref: http://www.marvell.com/products/processors/applications/armada_100
>
> SoC versions Supported:
> 1) ARMADA168/88AP168    (Aspen P)
> 2) ARMADA166/88AP166    (Aspen M)
> 3) ARMADA162/88AP162    (Aspen L)
>
> Contributors:
> Eric Miao <eric.y.miao@marvell.com>

<eric.miao@marvell.com>

Or

<eric.y.miao@gmail.com>

Actually I have little contribution to this, // red face.

The patch below seems quite good. I'll be glad to see this be
upstreamed in the u-boot tree.

> Lei Wen <leiwen@marvell.com>
> Mahavir Jain <mjain@marvell.com>
>
> Signed-off-by: Mahavir Jain <mjain@marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log V2:
> 1. C-struct used for dram.c
> 2. lib declaration changed from .a to .o
> 3. Implemented review feedback for v1
>
> Changelog V3:
> 1. timer variables in gt_t used insted of locally defined global variables
> 2. register global pointer moved to respective functions
> 3. Macro READ_TIMER converted to function read_timer()
> 4. c-struc in armada100.h fixed for wrong padding
>
> Changelog V4:
> 1. timer.c updated for build warning
>
>  arch/arm/cpu/arm926ejs/armada100/Makefile       |   46 +++++
>  arch/arm/cpu/arm926ejs/armada100/cpu.c          |   92 ++++++++++
>  arch/arm/cpu/arm926ejs/armada100/dram.c         |  131 ++++++++++++++
>  arch/arm/cpu/arm926ejs/armada100/timer.c        |  207 +++++++++++++++++++++++
>  arch/arm/include/asm/arch-armada100/armada100.h |  121 +++++++++++++
>  arch/arm/include/asm/arch-armada100/cpu.h       |   53 ++++++
>  6 files changed, 650 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
>  create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
>  create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
>
> diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
> new file mode 100644
> index 0000000..76bd06d
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
> @@ -0,0 +1,46 @@
> +#
> +# (C) Copyright 2010
> +# Marvell Semiconductor <www.marvell.com>
> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB    = $(obj)lib$(SOC).o
> +
> +COBJS-y        = cpu.o timer.o dram.o
> +
> +SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
> +
> +all:   $(obj).depend $(LIB)
> +
> +$(LIB):        $(OBJS)
> +       $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
> new file mode 100644
> index 0000000..62aa175
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
> @@ -0,0 +1,92 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/armada100.h>
> +#include <asm/io.h>
> +
> +#define UARTCLK14745KHZ        (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
> +#define SET_MRVL_ID    (1<<8)
> +#define L2C_RAM_SEL    (1<<4)
> +
> +int arch_cpu_init(void)
> +{
> +       u32 val;
> +       struct armd1cpu_registers *cpuregs =
> +               (struct armd1cpu_registers *) ARMD1_CPU_BASE;
> +
> +       struct armd1apb1_registers *apb1clkres =
> +               (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
> +
> +       struct armd1mpmu_registers *mpmu =
> +               (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
> +
> +       /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
> +       val = readl(&cpuregs->cpu_conf);
> +       val = val | SET_MRVL_ID;
> +       writel(val, &cpuregs->cpu_conf);
> +
> +       /* Enable Clocks for all hardware units */
> +       writel(0xFFFFFFFF, &mpmu->acgr);
> +
> +       /* Turn on AIB and AIB-APB Functional clock */
> +       writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
> +
> +       /* ensure L2 cache is not mapped as SRAM */
> +       val = readl(&cpuregs->cpu_conf);
> +       val = val & ~(L2C_RAM_SEL);
> +       writel(val, &cpuregs->cpu_conf);
> +
> +       /* Enable GPIO clock */
> +       writel(APBC_APBCLK, &apb1clkres->gpio);
> +
> +       /*
> +        * Enable Functional and APB clock at 14.7456MHz
> +        * for configured UART console
> +        */
> +#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
> +       writel(UARTCLK14745KHZ, &apb1clkres->uart3);
> +#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
> +       writel(UARTCLK14745KHZ, &apb1clkres->uart2);
> +#else
> +       writel(UARTCLK14745KHZ, &apb1clkres->uart1);
> +#endif
> +       icache_enable();
> +
> +       return 0;
> +}
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> +       u32 id;
> +       struct armd1cpu_registers *cpuregs =
> +               (struct armd1cpu_registers *) ARMD1_CPU_BASE;
> +
> +       id = readl(&cpuregs->chip_id);
> +       printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
> +       return 0;
> +}
> +#endif
> diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
> new file mode 100644
> index 0000000..eacec23
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
> @@ -0,0 +1,131 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/armada100.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * ARMADA100 DRAM controller supports upto 8 banks
> + * for chip select 0 and 1
> + */
> +
> +/*
> + * DDR Memory Control Registers
> + * Refer Datasheet Appendix A.17
> + */
> +struct armd1ddr_map_registers {
> +       u32     cs;     /* Memory Address Map Register -CS */
> +       u32     pad[3];
> +};
> +
> +struct armd1ddr_registers {
> +       u8      pad[0x100 - 0x000];
> +       struct armd1ddr_map_registers mmap[2];
> +};
> +
> +/*
> + * armd1_sdram_base - reads SDRAM Base Address Register
> + */
> +u32 armd1_sdram_base(int chip_sel)
> +{
> +       struct armd1ddr_registers *ddr_regs =
> +               (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
> +       u32 result = 0;
> +       u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
> +
> +       if (!CS_valid)
> +               return 0;
> +
> +       result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
> +       return result;
> +}
> +
> +/*
> + * armd1_sdram_size - reads SDRAM size
> + */
> +u32 armd1_sdram_size(int chip_sel)
> +{
> +       struct armd1ddr_registers *ddr_regs =
> +               (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
> +       u32 result = 0;
> +       u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
> +
> +       if (!CS_valid)
> +               return 0;
> +
> +       result = readl(&ddr_regs->mmap[chip_sel].cs);
> +       result = (result >> 16) & 0xF;
> +       if (result < 0x7) {
> +               printf("Unknown DRAM Size\n");
> +               return -1;
> +       } else {
> +               return ((0x8 << (result - 0x7)) * 1024 * 1024);
> +       }
> +}
> +
> +#ifndef CONFIG_SYS_BOARD_DRAM_INIT
> +int dram_init(void)
> +{
> +       int i;
> +
> +       gd->ram_size = 0;
> +       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> +               gd->bd->bi_dram[i].start = armd1_sdram_base(i);
> +               gd->bd->bi_dram[i].size = armd1_sdram_size(i);
> +               /*
> +                * It is assumed that all memory banks are consecutive
> +                * and without gaps.
> +                * If the gap is found, ram_size will be reported for
> +                * consecutive memory only
> +                */
> +               if (gd->bd->bi_dram[i].start != gd->ram_size)
> +                       break;
> +
> +               gd->ram_size += gd->bd->bi_dram[i].size;
> +
> +       }
> +
> +       for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> +               /* If above loop terminated prematurely, we need to set
> +                * remaining banks' start address & size as 0. Otherwise other
> +                * u-boot functions and Linux kernel gets wrong values which
> +                * could result in crash */
> +               gd->bd->bi_dram[i].start = 0;
> +               gd->bd->bi_dram[i].size = 0;
> +       }
> +       return 0;
> +}
> +
> +/*
> + * If this function is not defined here,
> + * board.c alters dram bank zero configuration defined above.
> + */
> +void dram_init_banksize(void)
> +{
> +       dram_init();
> +}
> +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
> diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
> new file mode 100644
> index 0000000..5d911c5
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
> @@ -0,0 +1,207 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/armada100.h>
> +
> +/*
> + * Timer registers
> + * Refer Section A.6 in Datasheet
> + */
> +struct armd1tmr_registers {
> +       u32 clk_ctrl;   /* Timer clk control reg */
> +       u32 match[9];   /* Timer match registers */
> +       u32 count[3];   /* Timer count registers */
> +       u32 status[3];
> +       u32 ie[3];
> +       u32 preload[3]; /* Timer preload value */
> +       u32 preload_ctrl[3];
> +       u32 wdt_match_en;
> +       u32 wdt_match_r;
> +       u32 wdt_val;
> +       u32 wdt_sts;
> +       u32 icr[3];
> +       u32 wdt_icr;
> +       u32 cer;        /* Timer count enable reg */
> +       u32 cmr;
> +       u32 ilr[3];
> +       u32 wcr;
> +       u32 wfar;
> +       u32 wsar;
> +       u32 cvwr;
> +};
> +
> +#define TIMER                  0       /* Use TIMER 0 */
> +/* Each timer has 3 match registers */
> +#define MATCH_CMP(x)           ((3 * TIMER) + x)
> +#define TIMER_LOAD_VAL                 0xffffffff
> +#define        COUNT_RD_REQ            0x1
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +/* Using gd->tbu from timestamp and gd->tbl for lastdec */
> +
> +/* For preventing risk of instability in reading counter value,
> + * first set read request to register cvwr and then read same
> + * register after it captures counter value.
> + */
> +ulong read_timer(void)
> +{
> +       struct armd1tmr_registers *armd1timers =
> +               (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
> +       volatile int loop=100;
> +
> +       writel(COUNT_RD_REQ, &armd1timers->cvwr);
> +       while (loop--);
> +       return(readl(&armd1timers->cvwr));
> +}
> +
> +void reset_timer_masked(void)
> +{
> +       /* reset time */
> +       gd->tbl = read_timer();
> +       gd->tbu = 0;
> +}
> +
> +ulong get_timer_masked(void)
> +{
> +       ulong now = read_timer();
> +
> +       if (now >= gd->tbl) {
> +               /* normal mode */
> +               gd->tbu += now - gd->tbl;
> +       } else {
> +               /* we have an overflow ... */
> +               gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
> +       }
> +       gd->tbl = now;
> +
> +       return gd->tbu;
> +}
> +
> +void reset_timer(void)
> +{
> +       reset_timer_masked();
> +}
> +
> +ulong get_timer(ulong base)
> +{
> +       return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
> +               base);
> +}
> +
> +void set_timer(ulong t)
> +{
> +       gd->tbu = t;
> +}
> +
> +void __udelay(unsigned long usec)
> +{
> +       ulong delayticks;
> +       ulong endtime;
> +
> +       delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
> +       endtime = get_timer_masked() + delayticks;
> +
> +       while (get_timer_masked() < endtime);
> +}
> +
> +/*
> + * init the Timer
> + */
> +int timer_init(void)
> +{
> +       struct armd1apb1_registers *apb1clkres =
> +               (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
> +       struct armd1tmr_registers *armd1timers =
> +               (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
> +
> +       /* Enable Timer clock at 3.25 MHZ */
> +       writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
> +
> +       /* load value into timer */
> +       writel(0x0, &armd1timers->clk_ctrl);
> +       /* Use Timer 0 Match Resiger 0 */
> +       writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
> +       /* Preload value is 0 */
> +       writel(0x0, &armd1timers->preload[TIMER]);
> +       /* Enable match comparator 0 for Timer 0 */
> +       writel(0x1, &armd1timers->preload_ctrl[TIMER]);
> +
> +       /* Enable timer 0 */
> +       writel(0x1, &armd1timers->cer);
> +       /* init the gd->tbu and gd->tbl value */
> +       reset_timer_masked();
> +
> +       return 0;
> +}
> +
> +#define MPMU_APRR_WDTR (1<<4)
> +#define TMR_WFAR       0xbaba  /* WDT Register First key */
> +#define TMP_WSAR       0xeb10  /* WDT Register Second key */
> +
> +/*
> + * This function uses internal Watchdog Timer
> + * based reset mechanism.
> + * Steps to write watchdog registers (protected access)
> + * 1. Write key value to TMR_WFAR reg.
> + * 2. Write key value to TMP_WSAR reg.
> + * 3. Perform write operation.
> + */
> +void reset_cpu (unsigned long ignored)
> +{
> +       struct armd1mpmu_registers *mpmu =
> +               (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
> +       struct armd1tmr_registers *armd1timers =
> +               (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
> +       u32 val;
> +
> +       /* negate hardware reset to the WDT after system reset */
> +       val = readl(&mpmu->aprr);
> +       val = val | MPMU_APRR_WDTR;
> +       writel(val, &mpmu->aprr);
> +
> +       /* reset/enable WDT clock */
> +       writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
> +       readl(&mpmu->wdtpcr);
> +       writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
> +       readl(&mpmu->wdtpcr);
> +
> +       /* clear previous WDT status */
> +       writel(TMR_WFAR, &armd1timers->wfar);
> +       writel(TMP_WSAR, &armd1timers->wsar);
> +       writel(0, &armd1timers->wdt_sts);
> +
> +       /* set match counter */
> +       writel(TMR_WFAR, &armd1timers->wfar);
> +       writel(TMP_WSAR, &armd1timers->wsar);
> +       writel(0xf, &armd1timers->wdt_match_r);
> +
> +       /* enable WDT reset */
> +       writel(TMR_WFAR, &armd1timers->wfar);
> +       writel(TMP_WSAR, &armd1timers->wsar);
> +       writel(0x3, &armd1timers->wdt_match_en);
> +
> +       while(1);
> +}
> diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
> new file mode 100644
> index 0000000..d5d125a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armada100/armada100.h
> @@ -0,0 +1,121 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ASM_ARCH_ARMADA100_H
> +#define _ASM_ARCH_ARMADA100_H
> +
> +#ifndef __ASSEMBLY__
> +#include <asm/types.h>
> +#include <asm/io.h>
> +#endif /* __ASSEMBLY__ */
> +
> +#if defined (CONFIG_ARMADA100)
> +#include <asm/arch/cpu.h>
> +
> +/* Common APB clock register bit definitions */
> +#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
> +#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
> +#define APBC_RST        (1<<2)  /* Reset Generation */
> +/* Functional Clock Selection Mask */
> +#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
> +
> +/* Register Base Addresses */
> +#define ARMD1_DRAM_BASE                0xB0000000
> +#define ARMD1_TIMER_BASE       0xD4014000
> +#define ARMD1_APBC1_BASE       0xD4015000
> +#define ARMD1_APBC2_BASE       0xD4015800
> +#define ARMD1_UART1_BASE       0xD4017000
> +#define ARMD1_UART2_BASE       0xD4018000
> +#define ARMD1_GPIO_BASE                0xD4019000
> +#define ARMD1_SSP1_BASE                0xD401B000
> +#define ARMD1_SSP2_BASE                0xD401C000
> +#define ARMD1_MFPR_BASE                0xD401E000
> +#define ARMD1_SSP3_BASE                0xD401F000
> +#define ARMD1_SSP4_BASE                0xD4020000
> +#define ARMD1_SSP5_BASE                0xD4021000
> +#define ARMD1_UART3_BASE       0xD4026000
> +#define ARMD1_MPMU_BASE                0xD4050000
> +#define ARMD1_APMU_BASE                0xD4282800
> +#define ARMD1_CPU_BASE         0xD4282C00
> +
> +/*
> + * Main Power Management (MPMU) Registers
> + * Refer Datasheet Appendix A.8
> + */
> +struct armd1mpmu_registers {
> +       u8 pad0[0x08 - 0x00];
> +       u32 fccr;       /*0x0008*/
> +       u32 pocr;       /*0x000c*/
> +       u32 posr;       /*0x0010*/
> +       u32 succr;      /*0x0014*/
> +       u8 pad1[0x030 - 0x014 - 4];
> +       u32 gpcr;       /*0x0030*/
> +       u8 pad2[0x200 - 0x030 - 4];
> +       u32 wdtpcr;     /*0x0200*/
> +       u8 pad3[0x1000 - 0x200 - 4];
> +       u32 apcr;       /*0x1000*/
> +       u32 apsr;       /*0x1004*/
> +       u8 pad4[0x1020 - 0x1004 - 4];
> +       u32 aprr;       /*0x1020*/
> +       u32 acgr;       /*0x1024*/
> +       u32 arsr;       /*0x1028*/
> +};
> +
> +/*
> + * APB1 Clock Reset/Control Registers
> + * Refer Datasheet Appendix A.10
> + */
> +struct armd1apb1_registers {
> +       u32 uart1;      /*0x000*/
> +       u32 uart2;      /*0x004*/
> +       u32 gpio;       /*0x008*/
> +       u32 pwm1;       /*0x00c*/
> +       u32 pwm2;       /*0x010*/
> +       u32 pwm3;       /*0x014*/
> +       u32 pwm4;       /*0x018*/
> +       u8 pad0[0x028 - 0x018 - 4];
> +       u32 rtc;        /*0x028*/
> +       u32 twsi0;      /*0x02c*/
> +       u32 kpc;        /*0x030*/
> +       u32 timers;     /*0x034*/
> +       u8 pad1[0x03c - 0x034 - 4];
> +       u32 aib;        /*0x03c*/
> +       u32 sw_jtag;    /*0x040*/
> +       u32 timer1;     /*0x044*/
> +       u32 onewire;    /*0x048*/
> +       u8 pad2[0x050 - 0x048 - 4];
> +       u32 asfar;      /*0x050 AIB Secure First Access Reg*/
> +       u32 assar;      /*0x054 AIB Secure Second Access Reg*/
> +       u8 pad3[0x06c - 0x054 - 4];
> +       u32 twsi1;      /*0x06c*/
> +       u32 uart3;      /*0x070*/
> +       u8 pad4[0x07c - 0x070 - 4];
> +       u32 timer2;     /*0x07C*/
> +       u8 pad5[0x084 - 0x07c - 4];
> +       u32 ac97;       /*0x084*/
> +};
> +
> +#endif /* CONFIG_ARMADA100 */
> +#endif /* _ASM_ARCH_ARMADA100_H */
> diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
> new file mode 100644
> index 0000000..0518a6a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armada100/cpu.h
> @@ -0,0 +1,53 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ARMADA100CPU_H
> +#define _ARMADA100CPU_H
> +
> +#include <asm/io.h>
> +#include <asm/system.h>
> +
> +/*
> + * CPU Interface Registers
> + * Refer Datasheet Appendix A.2
> + */
> +struct armd1cpu_registers {
> +       u32 chip_id;            /* Chip Id Reg */
> +       u32 pad;
> +       u32 cpu_conf;           /* CPU Conf Reg */
> +       u32 pad1;
> +       u32 cpu_sram_spd;       /* CPU SRAM Speed Reg */
> +       u32 pad2;
> +       u32 cpu_l2c_spd;        /* CPU L2cache Speed Conf */
> +       u32 mcb_conf;           /* MCB Conf Reg */
> +       u32 sys_boot_ctl;       /* Sytem Boot Control */
> +};
> +
> +/*
> + * Functions
> + */
> +u32 armd1_sdram_base(int);
> +u32 armd1_sdram_size(int);
> +
> +#endif /* _ARMADA100CPU_H */
> --
> 1.5.3.4
>
>
Prafulla Wadaskar - Dec. 8, 2010, 5:19 a.m.
> -----Original Message-----
> From: Eric Miao [mailto:eric.y.miao@gmail.com]
> Sent: Wednesday, December 08, 2010 8:03 AM
> To: Prafulla Wadaskar
> Cc: u-boot@lists.denx.de; Lei Wen; Yu Tang; Kiran Vedere; Manas Saksena;
> Prabhanjan Sarnaik; Ashish Karkare; Mahavir Jain
> Subject: Re: [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100
> Familiy SoCs
> 
> On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com>
> wrote:
> > ARMADA 100 Family processors are highly integrated SoCs
> > based on Sheeva_88SV331x-v5 PJ1 cpu core.
> > Ref: http://www.marvell.com/products/processors/applications/armada_100
> >
> > SoC versions Supported:
> > 1) ARMADA168/88AP168    (Aspen P)
> > 2) ARMADA166/88AP166    (Aspen M)
> > 3) ARMADA162/88AP162    (Aspen L)
> >
> > Contributors:
> > Eric Miao <eric.y.miao@marvell.com>
> 
> <eric.miao@marvell.com>
> 
> Or
> 
> <eric.y.miao@gmail.com>

Hi Eric
I will correct this.

> 
> Actually I have little contribution to this, // red face.

Something is always better than nothing :-)

> 
> The patch below seems quite good. I'll be glad to see this be
> upstreamed in the u-boot tree.

Thanks, hope it will happen soon.

Regards..
Prafulla ..
Prafulla Wadaskar - Dec. 11, 2010, 2:12 p.m.
> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla@marvell.com]
> Sent: Tuesday, December 07, 2010 10:36 PM
> To: u-boot@lists.denx.de
> Cc: Lei Wen; Eric Miao; Yu Tang; Kiran Vedere; Manas Saksena; Prabhanjan
> Sarnaik; Ashish Karkare; Prafulla Wadaskar; Mahavir Jain
> Subject: [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy
> SoCs
> 
> ARMADA 100 Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref: http://www.marvell.com/products/processors/applications/armada_100
> 
> SoC versions Supported:
> 1) ARMADA168/88AP168	(Aspen P)
> 2) ARMADA166/88AP166	(Aspen M)
> 3) ARMADA162/88AP162	(Aspen L)
> 
> Contributors:
> Eric Miao <eric.y.miao@marvell.com>
> Lei Wen <leiwen@marvell.com>
> Mahavir Jain <mjain@marvell.com>
> 
> Signed-off-by: Mahavir Jain <mjain@marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log V2:
> 1. C-struct used for dram.c
> 2. lib declaration changed from .a to .o
> 3. Implemented review feedback for v1
> 
> Changelog V3:
> 1. timer variables in gt_t used insted of locally defined global variables
> 2. register global pointer moved to respective functions
> 3. Macro READ_TIMER converted to function read_timer()
> 4. c-struc in armada100.h fixed for wrong padding
> 
> Changelog V4:
> 1. timer.c updated for build warning
> 
>  arch/arm/cpu/arm926ejs/armada100/Makefile       |   46 +++++
>  arch/arm/cpu/arm926ejs/armada100/cpu.c          |   92 ++++++++++
>  arch/arm/cpu/arm926ejs/armada100/dram.c         |  131 ++++++++++++++
>  arch/arm/cpu/arm926ejs/armada100/timer.c        |  207
> +++++++++++++++++++++++
>  arch/arm/include/asm/arch-armada100/armada100.h |  121 +++++++++++++
>  arch/arm/include/asm/arch-armada100/cpu.h       |   53 ++++++
>  6 files changed, 650 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
>  create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
>  create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
>

Applied to u-boot-marvell.git master branch

Regards..
Prafulla ..

Patch

diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
new file mode 100644
index 0000000..76bd06d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
@@ -0,0 +1,46 @@ 
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	= cpu.o timer.o dram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
new file mode 100644
index 0000000..62aa175
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -0,0 +1,92 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable Clocks for all hardware units */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on AIB and AIB-APB Functional clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+	/* ensure L2 cache is not mapped as SRAM */
+	val = readl(&cpuregs->cpu_conf);
+	val = val & ~(L2C_RAM_SEL);
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apb1clkres->gpio);
+
+	/*
+	 * Enable Functional and APB clock at 14.7456MHz
+	 * for configured UART console
+	 */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
new file mode 100644
index 0000000..eacec23
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -0,0 +1,131 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd1ddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
new file mode 100644
index 0000000..5d911c5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -0,0 +1,207 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr;
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &armd1timers->cvwr);
+	while (loop--);
+	return(readl(&armd1timers->cvwr));
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd1timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd1timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &armd1timers->cer);
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0, &armd1timers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0xf, &armd1timers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0x3, &armd1timers->wdt_match_en);
+
+	while(1);
+}
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
new file mode 100644
index 0000000..d5d125a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -0,0 +1,121 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif	/* __ASSEMBLY__ */
+
+#if defined (CONFIG_ARMADA100)
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE		0xB0000000
+#define ARMD1_TIMER_BASE	0xD4014000
+#define ARMD1_APBC1_BASE	0xD4015000
+#define ARMD1_APBC2_BASE	0xD4015800
+#define ARMD1_UART1_BASE	0xD4017000
+#define ARMD1_UART2_BASE	0xD4018000
+#define ARMD1_GPIO_BASE		0xD4019000
+#define ARMD1_SSP1_BASE		0xD401B000
+#define ARMD1_SSP2_BASE		0xD401C000
+#define ARMD1_MFPR_BASE		0xD401E000
+#define ARMD1_SSP3_BASE		0xD401F000
+#define ARMD1_SSP4_BASE		0xD4020000
+#define ARMD1_SSP5_BASE		0xD4021000
+#define ARMD1_UART3_BASE	0xD4026000
+#define ARMD1_MPMU_BASE		0xD4050000
+#define ARMD1_APMU_BASE		0xD4282800
+#define ARMD1_CPU_BASE		0xD4282C00
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+	u8 pad0[0x08 - 0x00];
+	u32 fccr;	/*0x0008*/
+	u32 pocr;	/*0x000c*/
+	u32 posr;	/*0x0010*/
+	u32 succr;	/*0x0014*/
+	u8 pad1[0x030 - 0x014 - 4];
+	u32 gpcr;	/*0x0030*/
+	u8 pad2[0x200 - 0x030 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad3[0x1000 - 0x200 - 4];
+	u32 apcr;	/*0x1000*/
+	u32 apsr;	/*0x1004*/
+	u8 pad4[0x1020 - 0x1004 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+	u32 uart1;	/*0x000*/
+	u32 uart2;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u32 pwm1;	/*0x00c*/
+	u32 pwm2;	/*0x010*/
+	u32 pwm3;	/*0x014*/
+	u32 pwm4;	/*0x018*/
+	u8 pad0[0x028 - 0x018 - 4];
+	u32 rtc;	/*0x028*/
+	u32 twsi0;	/*0x02c*/
+	u32 kpc;	/*0x030*/
+	u32 timers;	/*0x034*/
+	u8 pad1[0x03c - 0x034 - 4];
+	u32 aib;	/*0x03c*/
+	u32 sw_jtag;	/*0x040*/
+	u32 timer1;	/*0x044*/
+	u32 onewire;	/*0x048*/
+	u8 pad2[0x050 - 0x048 - 4];
+	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
+	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
+	u8 pad3[0x06c - 0x054 - 4];
+	u32 twsi1;	/*0x06c*/
+	u32 uart3;	/*0x070*/
+	u8 pad4[0x07c - 0x070 - 4];
+	u32 timer2;	/*0x07C*/
+	u8 pad5[0x084 - 0x07c - 4];
+	u32 ac97;	/*0x084*/
+};
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
new file mode 100644
index 0000000..0518a6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/cpu.h
@@ -0,0 +1,53 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */