| Message ID | 1490879336-4995-15-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
On 03/30/2017 03:08 PM, Ley Foon Tan wrote: > Add SPL support for Arria 10. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- > arch/arm/mach-socfpga/spl.c | 74 ++++++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 69 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c > index fec4c7a..31f4d41 100644 > --- a/arch/arm/mach-socfpga/spl.c > +++ b/arch/arm/mach-socfpga/spl.c > @@ -19,23 +19,32 @@ > #include <asm/arch/sdram.h> > #include <asm/arch/scu.h> > #include <asm/arch/nic301.h> > +#include <asm/sections.h> > +#include <fdtdec.h> > +#include <watchdog.h> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +#include <asm/arch/pinmux.h> > +#endif > > DECLARE_GLOBAL_DATA_PTR; > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > static struct pl310_regs *const pl310 = > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > static struct scu_registers *scu_regs = > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; > static struct nic301_registers *nic301_regs = > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; > -static struct socfpga_system_manager *sysmgr_regs = > +#endif > + > +static const struct socfpga_system_manager *sysmgr_regs = > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > u32 spl_boot_device(void) > { > const u32 bsel = readl(&sysmgr_regs->bootinfo); > > - switch (bsel & 0x7) { > + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { > case 0x1: /* FPGA (HPS2FPGA Bridge) */ > return BOOT_DEVICE_RAM; > case 0x2: /* NAND Flash (1.8V) */ > @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device) > } > #endif > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > static void socfpga_nic301_slave_ns(void) > { > writel(0x1, &nic301_regs->lwhps2fpgaregs); > @@ -85,6 +95,7 @@ void board_init_f(ulong dummy) > #endif > unsigned long sdram_size; > unsigned long reg; > + int ret; > > /* > * First C code to run. Clear fake OCRAM ECC first as SBE > @@ -117,7 +128,11 @@ void board_init_f(ulong dummy) > /* Put everything into reset but L4WD0. */ > socfpga_per_reset_all(); > /* Put FPGA bridges into reset too. */ > - socfpga_bridges_reset(1); > + ret = socfpga_bridges_reset(1); > + if (ret) { > + debug("socfpga_bridges_reset() failed: %d\n", ret); Shouldn't this be printf() ? > + hang(); > + } > > socfpga_per_reset(SOCFPGA_RESET(SDR), 0); > socfpga_per_reset(SOCFPGA_RESET(UART0), 0); > @@ -147,7 +162,11 @@ void board_init_f(ulong dummy) > > /* De-assert reset for peripherals and bridges based on handoff */ > reset_deassert_peripherals_handoff(); > - socfpga_bridges_reset(0); > + ret = socfpga_bridges_reset(0); > + if (ret) { > + debug("socfpga_bridges_reset() failed: %d\n", ret); DTTO ? > + hang(); > + } > > debug("Unfreezing/Thaw all I/O banks\n"); > /* unfreeze / thaw all IO banks */ > @@ -177,8 +196,53 @@ void board_init_f(ulong dummy) > hang(); > } > > - socfpga_bridges_reset(1); > + ret = socfpga_bridges_reset(1); > + if (ret) { > + debug("socfpga_bridges_reset() failed: %d\n", ret); DTTO ? > + hang(); > + } > > /* Configure simple malloc base pointer into RAM. */ > gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); > } > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +#ifdef CONFIG_SPL_BOARD_INIT > +void spl_board_init(void) > +{ > + /* configuring the clock based on handoff */ > + cm_basic_init(gd->fdt_blob); > + WATCHDOG_RESET(); > + > + config_dedicated_pins(gd->fdt_blob); > + WATCHDOG_RESET(); > + > + /* Release UART from reset */ > + socfpga_reset_uart(0); > + > + /* enable console uart printing */ > + preloader_console_init(); > +} > +#endif > + > +void board_init_f(ulong dummy) > +{ > + /* > + * Configure Clock Manager to use intosc clock instead external osc to > + * ensure success watchdog operation. We do it as early as possible. > + */ > + cm_use_intosc(); > + > + socfpga_watchdog_disable(); > + > + arch_early_init_r(); > + > +#ifdef CONFIG_HW_WATCHDOG > + /* release osc1 watchdog timer 0 from reset */ > + socfpga_reset_deassert_osc1wd0(); > + > + /* reconfigure and enable the watchdog */ > + hw_watchdog_init(); > + WATCHDOG_RESET(); > +#endif /* CONFIG_HW_WATCHDOG */ > +} > +#endif >
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a..31f4d41 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -19,23 +19,32 @@ #include <asm/arch/sdram.h> #include <asm/arch/scu.h> #include <asm/arch/nic301.h> +#include <asm/sections.h> +#include <fdtdec.h> +#include <watchdog.h> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/pinmux.h> +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo); - switch (bsel & 0x7) { + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -85,6 +95,7 @@ void board_init_f(ulong dummy) #endif unsigned long sdram_size; unsigned long reg; + int ret; /* * First C code to run. Clear fake OCRAM ECC first as SBE @@ -117,7 +128,11 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */ - socfpga_bridges_reset(1); + ret = socfpga_bridges_reset(1); + if (ret) { + debug("socfpga_bridges_reset() failed: %d\n", ret); + hang(); + } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); @@ -147,7 +162,11 @@ void board_init_f(ulong dummy) /* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); - socfpga_bridges_reset(0); + ret = socfpga_bridges_reset(0); + if (ret) { + debug("socfpga_bridges_reset() failed: %d\n", ret); + hang(); + } debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ @@ -177,8 +196,53 @@ void board_init_f(ulong dummy) hang(); } - socfpga_bridges_reset(1); + ret = socfpga_bridges_reset(1); + if (ret) { + debug("socfpga_bridges_reset() failed: %d\n", ret); + hang(); + } /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + socfpga_reset_uart(0); + + /* enable console uart printing */ + preloader_console_init(); +} +#endif + +void board_init_f(ulong dummy) +{ + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + socfpga_watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + socfpga_reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ +} +#endif