From patchwork Mon Dec 6 16:13:33 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joern Rennecke X-Patchwork-Id: 74383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 709F8B70B8 for ; Tue, 7 Dec 2010 03:13:51 +1100 (EST) Received: (qmail 20766 invoked by alias); 6 Dec 2010 16:13:47 -0000 Received: (qmail 20751 invoked by uid 22791); 6 Dec 2010 16:13:43 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL, BAYES_00, KAM_STOCKGEN, MIME_QP_LONG_LINE, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from c60.cesmail.net (HELO c60.cesmail.net) (216.154.195.49) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 06 Dec 2010 16:13:36 +0000 Received: from unknown (HELO epsilon2) ([192.168.1.60]) by c60.cesmail.net with ESMTP; 06 Dec 2010 11:13:33 -0500 Received: from 89.241.159.65 ([89.241.159.65]) by webmail.spamcop.net (Horde MIME library) with HTTP; Mon, 06 Dec 2010 11:13:33 -0500 Message-ID: <20101206111333.q6h2g979xk4kw4g4-nzlynne@webmail.spamcop.net> Date: Mon, 06 Dec 2010 11:13:33 -0500 From: Joern Rennecke To: Andrew Pinski , gcc-patches@gcc.gnu.org Subject: RFA: Fix frv --enable-werror-always build on 64 bit hosts - take two References: <20101201193006.4c5mnv9j408s0coo-nzlynne@webmail.spamcop.net> In-Reply-To: MIME-Version: 1.0 User-Agent: Internet Messaging Program (IMP) H3 (4.1.4) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Quoting Andrew Pinski : > On Wed, Dec 1, 2010 at 4:30 PM, Joern Rennecke wrote: >> By using an inline function instead of a macro, warnings for 'always true' >> comparisons are avoided. >> > > How about using the IN_RANGE macro from system.h instead of having a new one? The frv.h IN_RANGE_P can do empty ranges (at the cost of sign-change-crossing ranges), but that isn't used by any of the 60 places where it is used. (FWIW, the sh64 gdb used to have conditionally empty ranges.) So, indeed, IN_RANGE appears to be a suitable substitute. cross-built on x86_64-pc-linux-gnu 2010-12-06 Joern Rennecke * config/frv/predicates.md (gpr_or_int12_operand): Use IN_RANGE. (gpr_fpr_or_int12_operand, gpr_or_int10_operand): Likewise. (int12_operand, int_2word_operand, uint16_operand): Likewise. (fpr_or_int6_operand, int6_operand, int5_operand): Likewise. (uint5_operand, uint4_operand): Likewise. * config/frv/frv.h (IN_RANGE_P): Delete. (GPR_P, FPR_P, CC_P, ICC_P, FCC_P, CR_P, ICR_P, FCR_P): Use IN_RANGE. (ACC_P, ACCG_P, SPR_P, CONST_OK_FOR_I, CONST_OK_FOR_J): Likewise. (CONST_OK_FOR_L, CONST_OK_FOR_M, CONST_OK_FOR_N): Likewise. (CONST_OK_FOR_P): Likewise. * config/frv/frv.md (*movqicc_internal2_int): Likewise. (*movqicc_internal2_float, *movhicc_internal2_int): Likewise. (*movhicc_internal2_float, *movsicc_internal2_int): Likewise. (*movsicc_internal2_float, casesi): Likewise. * config/frv/frv.c (frv_frame_offset_rtx): Likewise. (frv_asm_output_mi_thunk, frv_legitimate_address_p_1): Likewise. (frv_emit_movsi, output_move_single, frv_emit_cond_move): Likewise. (frv_split_cond_move, frv_rtx_costs): Likewise. Index: config/frv/predicates.md =================================================================== --- config/frv/predicates.md (revision 167494) +++ config/frv/predicates.md (working copy) @@ -110,7 +110,7 @@ (define_predicate "gpr_or_int12_operand" (match_code "reg,subreg,const_int,const") { if (GET_CODE (op) == CONST_INT) - return IN_RANGE_P (INTVAL (op), -2048, 2047); + return IN_RANGE (INTVAL (op), -2048, 2047); if (got12_operand (op, mode)) return true; @@ -141,7 +141,7 @@ (define_predicate "gpr_fpr_or_int12_oper int regno; if (GET_CODE (op) == CONST_INT) - return IN_RANGE_P (INTVAL (op), -2048, 2047); + return IN_RANGE (INTVAL (op), -2048, 2047); if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -170,7 +170,7 @@ (define_predicate "gpr_or_int10_operand" (match_code "reg,subreg,const_int") { if (GET_CODE (op) == CONST_INT) - return IN_RANGE_P (INTVAL (op), -512, 511); + return IN_RANGE (INTVAL (op), -512, 511); if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -493,7 +493,7 @@ (define_predicate "int12_operand" if (GET_CODE (op) != CONST_INT) return FALSE; - return IN_RANGE_P (INTVAL (op), -2048, 2047); + return IN_RANGE (INTVAL (op), -2048, 2047); }) ;; Return 1 if operand is an integer constant that takes 2 @@ -535,7 +535,7 @@ (define_predicate "int_2word_operand" return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op)); case CONST_INT: - return ! IN_RANGE_P (INTVAL (op), -32768, 32767); + return ! IN_RANGE (INTVAL (op), -32768, 32767); case CONST_DOUBLE: if (GET_MODE (op) == SFmode) @@ -543,12 +543,12 @@ (define_predicate "int_2word_operand" REAL_VALUE_FROM_CONST_DOUBLE (rv, op); REAL_VALUE_TO_TARGET_SINGLE (rv, l); value = l; - return ! IN_RANGE_P (value, -32768, 32767); + return ! IN_RANGE (value, -32768, 32767); } else if (GET_MODE (op) == VOIDmode) { value = CONST_DOUBLE_LOW (op); - return ! IN_RANGE_P (value, -32768, 32767); + return ! IN_RANGE (value, -32768, 32767); } break; } @@ -1117,7 +1117,7 @@ (define_predicate "uint16_operand" if (GET_CODE (op) != CONST_INT) return FALSE; - return IN_RANGE_P (INTVAL (op), 0, 0xffff); + return IN_RANGE (INTVAL (op), 0, 0xffff); }) ;; Returns 1 if OP is either a SYMBOL_REF or a constant. @@ -1444,7 +1444,7 @@ (define_predicate "fpr_or_int6_operand" (match_code "reg,subreg,const_int") { if (GET_CODE (op) == CONST_INT) - return IN_RANGE_P (INTVAL (op), -32, 31); + return IN_RANGE (INTVAL (op), -32, 31); if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -1471,7 +1471,7 @@ (define_predicate "int6_operand" if (GET_CODE (op) != CONST_INT) return FALSE; - return IN_RANGE_P (INTVAL (op), -32, 31); + return IN_RANGE (INTVAL (op), -32, 31); }) ;; Return 1 if operand is a 5-bit signed immediate. @@ -1479,7 +1479,7 @@ (define_predicate "int6_operand" (define_predicate "int5_operand" (match_code "const_int") { - return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15); + return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), -16, 15); }) ;; Return 1 if operand is a 5-bit unsigned immediate. @@ -1487,7 +1487,7 @@ (define_predicate "int5_operand" (define_predicate "uint5_operand" (match_code "const_int") { - return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31); + return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 31); }) ;; Return 1 if operand is a 4-bit unsigned immediate. @@ -1495,7 +1495,7 @@ (define_predicate "uint5_operand" (define_predicate "uint4_operand" (match_code "const_int") { - return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15); + return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 15); }) ;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1). @@ -1503,7 +1503,7 @@ (define_predicate "uint4_operand" (define_predicate "uint1_operand" (match_code "const_int") { - return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1); + return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 1); }) ;; Return 1 if operand is a valid ACC register number. Index: config/frv/frv.h =================================================================== --- config/frv/frv.h (revision 167494) +++ config/frv/frv.h (working copy) @@ -26,12 +26,6 @@ /* Frv general purpose macros. */ /* Align an address. */ #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1)) - -/* Return true if a value is inside a range. */ -#define IN_RANGE_P(VALUE, LOW, HIGH) \ - ( (((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \ - && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) - /* Driver configuration. */ @@ -604,18 +598,18 @@ #define CONSTANT_ALIGNMENT(EXP, ALIGN) #define IACC_FIRST (SPR_FIRST + 2) #define IACC_LAST (SPR_FIRST + 3) -#define GPR_P(R) IN_RANGE_P (R, GPR_FIRST, GPR_LAST) +#define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST) #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM) -#define FPR_P(R) IN_RANGE_P (R, FPR_FIRST, FPR_LAST) -#define CC_P(R) IN_RANGE_P (R, CC_FIRST, CC_LAST) -#define ICC_P(R) IN_RANGE_P (R, ICC_FIRST, ICC_LAST) -#define FCC_P(R) IN_RANGE_P (R, FCC_FIRST, FCC_LAST) -#define CR_P(R) IN_RANGE_P (R, CR_FIRST, CR_LAST) -#define ICR_P(R) IN_RANGE_P (R, ICR_FIRST, ICR_LAST) -#define FCR_P(R) IN_RANGE_P (R, FCR_FIRST, FCR_LAST) -#define ACC_P(R) IN_RANGE_P (R, ACC_FIRST, ACC_LAST) -#define ACCG_P(R) IN_RANGE_P (R, ACCG_FIRST, ACCG_LAST) -#define SPR_P(R) IN_RANGE_P (R, SPR_FIRST, SPR_LAST) +#define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST) +#define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST) +#define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST) +#define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST) +#define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST) +#define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST) +#define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST) +#define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST) +#define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST) +#define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST) #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) @@ -1166,21 +1160,21 @@ #define SECONDARY_OUTPUT_RELOAD_CLASS(CL #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x))) /* 6-bit signed immediate. */ -#define CONST_OK_FOR_I(VALUE) IN_RANGE_P(VALUE, -32, 31) +#define CONST_OK_FOR_I(VALUE) IN_RANGE (VALUE, -32, 31) /* 10-bit signed immediate. */ -#define CONST_OK_FOR_J(VALUE) IN_RANGE_P(VALUE, -512, 511) +#define CONST_OK_FOR_J(VALUE) IN_RANGE (VALUE, -512, 511) /* Unused */ #define CONST_OK_FOR_K(VALUE) 0 /* 16-bit signed immediate. */ -#define CONST_OK_FOR_L(VALUE) IN_RANGE_P(VALUE, -32768, 32767) +#define CONST_OK_FOR_L(VALUE) IN_RANGE (VALUE, -32768, 32767) /* 16-bit unsigned immediate. */ -#define CONST_OK_FOR_M(VALUE) IN_RANGE_P (VALUE, 0, 65535) +#define CONST_OK_FOR_M(VALUE) IN_RANGE (VALUE, 0, 65535) /* 12-bit signed immediate that is negative. */ -#define CONST_OK_FOR_N(VALUE) IN_RANGE_P(VALUE, -2048, -1) +#define CONST_OK_FOR_N(VALUE) IN_RANGE (VALUE, -2048, -1) /* Zero */ #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0) /* 12-bit signed immediate that is negative. */ -#define CONST_OK_FOR_P(VALUE) IN_RANGE_P(VALUE, 1, 2047) +#define CONST_OK_FOR_P(VALUE) IN_RANGE (VALUE, 1, 2047) /* A C expression that defines the machine-dependent operand constraint letters (`I', `J', `K', .. 'P') that specify particular ranges of integer values. Index: config/frv/frv.md =================================================================== --- config/frv/frv.md (revision 167494) +++ config/frv/frv.md (working copy) @@ -4628,8 +4628,8 @@ (define_insn "*movqicc_internal2_int" (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] "(INTVAL (operands[3]) == 0 || INTVAL (operands[4]) == 0 - || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) - && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" + || (IN_RANGE (INTVAL (operands[3]), -2048, 2047) + && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" "#" [(set_attr "length" "8,12,8,12,12") (set_attr "type" "multi")]) @@ -4645,8 +4645,8 @@ (define_insn "*movqicc_internal2_float" "TARGET_HARD_FLOAT && (INTVAL (operands[3]) == 0 || INTVAL (operands[4]) == 0 - || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) - && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" + || (IN_RANGE (INTVAL (operands[3]), -2048, 2047) + && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" "#" [(set_attr "length" "8,12,8,12,12") (set_attr "type" "multi")]) @@ -4713,8 +4713,8 @@ (define_insn "*movhicc_internal2_int" (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] "(INTVAL (operands[3]) == 0 || INTVAL (operands[4]) == 0 - || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) - && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" + || (IN_RANGE (INTVAL (operands[3]), -2048, 2047) + && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" "#" [(set_attr "length" "8,12,8,12,12") (set_attr "type" "multi")]) @@ -4730,8 +4730,8 @@ (define_insn "*movhicc_internal2_float" "TARGET_HARD_FLOAT && (INTVAL (operands[3]) == 0 || INTVAL (operands[4]) == 0 - || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) - && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" + || (IN_RANGE (INTVAL (operands[3]), -2048, 2047) + && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" "#" [(set_attr "length" "8,12,8,12,12") (set_attr "type" "multi")]) @@ -4798,8 +4798,8 @@ (define_insn "*movsicc_internal2_int" (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] "(INTVAL (operands[3]) == 0 || INTVAL (operands[4]) == 0 - || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) - && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" + || (IN_RANGE (INTVAL (operands[3]), -2048, 2047) + && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" "#" [(set_attr "length" "8,12,8,12,12") (set_attr "type" "multi")]) @@ -4815,8 +4815,8 @@ (define_insn "*movsicc_internal2_float" "TARGET_HARD_FLOAT && (INTVAL (operands[3]) == 0 || INTVAL (operands[4]) == 0 - || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) - && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" + || (IN_RANGE (INTVAL (operands[3]), -2048, 2047) + && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" "#" [(set_attr "length" "8,12,8,12,12") (set_attr "type" "multi")]) @@ -5564,7 +5564,7 @@ (define_expand "casesi" gcc_assert (GET_CODE (operands[2]) == CONST_INT); /* If we can't generate an immediate instruction, promote to register. */ - if (! IN_RANGE_P (INTVAL (range), -2048, 2047)) + if (! IN_RANGE (INTVAL (range), -2048, 2047)) range = force_reg (SImode, range); /* If low bound is 0, we don't have to subtract it. */ @@ -5573,7 +5573,7 @@ (define_expand "casesi" else { indx = gen_reg_rtx (SImode); - if (IN_RANGE_P (INTVAL (low), -2047, 2048)) + if (IN_RANGE (INTVAL (low), -2047, 2048)) emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low)))); else emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low))); Index: config/frv/frv.c =================================================================== --- config/frv/frv.c (revision 167494) +++ config/frv/frv.c (working copy) @@ -1624,12 +1624,12 @@ frv_alloc_temp_reg ( frv_frame_offset_rtx (int offset) { rtx offset_rtx = GEN_INT (offset); - if (IN_RANGE_P (offset, -2048, 2047)) + if (IN_RANGE (offset, -2048, 2047)) return offset_rtx; else { rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); - if (IN_RANGE_P (offset, -32768, 32767)) + if (IN_RANGE (offset, -32768, 32767)) emit_insn (gen_movsi (reg_rtx, offset_rtx)); else { @@ -2057,7 +2057,7 @@ frv_asm_output_mi_thunk (FILE *file, const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); /* Do the add using an addi if possible. */ - if (IN_RANGE_P (delta, -2048, 2047)) + if (IN_RANGE (delta, -2048, 2047)) fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); else { @@ -3459,13 +3459,13 @@ frv_legitimate_address_p_1 (enum machine ret = FALSE; else { - ret = IN_RANGE_P (INTVAL (x), -2048, 2047); + ret = IN_RANGE (INTVAL (x), -2048, 2047); /* If we can't use load/store double operations, make sure we can address the second word. */ if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) - ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, - -2048, 2047); + ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1, + -2048, 2047); } break; @@ -3511,12 +3511,12 @@ frv_legitimate_address_p_1 (enum machine else { value = INTVAL (x1); - ret = IN_RANGE_P (value, -2048, 2047); + ret = IN_RANGE (value, -2048, 2047); /* If we can't use load/store double operations, make sure we can address the second word. */ if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) - ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); + ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); } break; @@ -4076,9 +4076,9 @@ frv_emit_movsi (rtx dest, rtx src) add instruction, so expose this to CSE by copying to an intermediate register. */ || (GET_CODE (src) == REG - && IN_RANGE_P (REGNO (src), - FIRST_VIRTUAL_REGISTER, - LAST_VIRTUAL_POINTER_REGISTER)))) + && IN_RANGE (REGNO (src), + FIRST_VIRTUAL_REGISTER, + LAST_VIRTUAL_POINTER_REGISTER)))) { emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); return TRUE; @@ -4380,7 +4380,7 @@ output_move_single (rtx operands[], rtx else value = CONST_DOUBLE_LOW (src); - if (IN_RANGE_P (value, -32768, 32767)) + if (IN_RANGE (value, -32768, 32767)) return "setlos %1, %0"; return "#"; @@ -4951,8 +4951,8 @@ frv_emit_cond_move (rtx dest, rtx test_r between the two fits in an addi's range, load up the difference, then conditionally move in 0, and then unconditionally add the first value. */ - else if (IN_RANGE_P (value1, -2048, 2047) - && IN_RANGE_P (value2 - value1, -2048, 2047)) + else if (IN_RANGE (value1, -2048, 2047) + && IN_RANGE (value2 - value1, -2048, 2047)) ; /* If neither condition holds, just force the constant into a @@ -5046,8 +5046,8 @@ frv_split_cond_move (rtx operands[]) between the two fits in an addi's range, load up the difference, then conditionally move in 0, and then unconditionally add the first value. */ - else if (IN_RANGE_P (value1, -2048, 2047) - && IN_RANGE_P (value2 - value1, -2048, 2047)) + else if (IN_RANGE (value1, -2048, 2047) + && IN_RANGE (value2 - value1, -2048, 2047)) { rtx dest_si = ((GET_MODE (dest) == SImode) ? dest @@ -9611,7 +9611,7 @@ frv_rtx_costs (rtx x, { case CONST_INT: /* Make 12-bit integers really cheap. */ - if (IN_RANGE_P (INTVAL (x), -2048, 2047)) + if (IN_RANGE (INTVAL (x), -2048, 2047)) { *total = 0; return true;