From patchwork Mon Dec 6 09:26:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Chouteau X-Patchwork-Id: 74329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 72BCFB70D6 for ; Mon, 6 Dec 2010 21:02:26 +1100 (EST) Received: from localhost ([127.0.0.1]:51568 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPXRq-0005Gj-6u for incoming@patchwork.ozlabs.org; Mon, 06 Dec 2010 04:33:30 -0500 Received: from [140.186.70.92] (port=37505 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPXLX-0003GO-LF for qemu-devel@nongnu.org; Mon, 06 Dec 2010 04:27:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PPXLU-0006UO-K4 for qemu-devel@nongnu.org; Mon, 06 Dec 2010 04:26:59 -0500 Received: from mel.act-europe.fr ([194.98.77.210]:32862) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PPXLU-0006UD-D0 for qemu-devel@nongnu.org; Mon, 06 Dec 2010 04:26:56 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id CA32ACB026E; Mon, 6 Dec 2010 10:26:43 +0100 (CET) X-Quarantine-ID: <2YIYzA-oxXOp> X-Virus-Scanned: amavisd-new at eu.adacore.com X-Amavis-Alert: BAD HEADER, Duplicate header field: "In-Reply-To" Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2YIYzA-oxXOp; Mon, 6 Dec 2010 10:26:43 +0100 (CET) Received: from PomPomGalli.act-europe.fr (pompomgalli.act-europe.fr [10.10.1.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id A9A3DCB029D; Mon, 6 Dec 2010 10:26:43 +0100 (CET) From: Fabien Chouteau To: qemu-devel@nongnu.org Date: Mon, 6 Dec 2010 10:26:07 +0100 Message-Id: <0c3c2a6386d496eab09ec18e16657c960ad3a9d0.1291397462.git.chouteau@adacore.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <7c24465a442966eba3ae4e2bb03da4463e0f8644.1291397462.git.chouteau@adacore.com> References: <5c4895c6f9c6ebd80262c494563726dd59a7ff93.1291397462.git.chouteau@adacore.com> <3ecbaf8fc01bebd2b2f2fb2c709642b2a1db7ff0.1291397462.git.chouteau@adacore.com> <7c24465a442966eba3ae4e2bb03da4463e0f8644.1291397462.git.chouteau@adacore.com> In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Fabien Chouteau Subject: [Qemu-devel] [PATCH 6/6] [RFC] SPARCV8 asr17 register support. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Fabien Chouteau --- hw/leon3.c | 6 ++++++ target-sparc/cpu.h | 1 + target-sparc/machine.c | 2 ++ target-sparc/translate.c | 10 ++++++++++ 4 files changed, 19 insertions(+), 0 deletions(-) diff --git a/hw/leon3.c b/hw/leon3.c index ba61081..9605ce8 100644 --- a/hw/leon3.c +++ b/hw/leon3.c @@ -187,6 +187,12 @@ static void main_cpu_reset(void *opaque) values */ leon3_state.inst_cache_conf = 0x10220000; leon3_state.data_cache_conf = 0x18220000; + + /* Asr17 for Leon3 mono-processor */ + env->asr17 &= 0 << 28; /* CPU id */ + env->asr17 &= 1 << 8; /* SPARC V8 multiply and divide available */ + env->asr17 &= env->nwindows -1; /* Number of implemented registers + windows */ } static void leon3_generic_hw_init(ram_addr_t ram_size, diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 6020ffd..36d49fc 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -341,6 +341,7 @@ typedef struct CPUSPARCState { from PSR) */ #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) uint32_t wim; /* window invalid mask */ + uint32_t asr17; /* asr17 */ #endif target_ulong tbr; /* trap base register */ #if !defined(TARGET_SPARC64) diff --git a/target-sparc/machine.c b/target-sparc/machine.c index 752e431..c530bd3 100644 --- a/target-sparc/machine.c +++ b/target-sparc/machine.c @@ -42,6 +42,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32s(f, &env->pil_in); #ifndef TARGET_SPARC64 qemu_put_be32s(f, &env->wim); + qemu_put_be32s(f, &env->asr17); /* MMU */ for (i = 0; i < 32; i++) qemu_put_be32s(f, &env->mmuregs[i]); @@ -138,6 +139,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be32s(f, &env->pil_in); #ifndef TARGET_SPARC64 qemu_get_be32s(f, &env->wim); + qemu_get_be32s(f, &env->asr17); /* MMU */ for (i = 0; i < 32; i++) qemu_get_be32s(f, &env->mmuregs[i]); diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 23f9519..65de614 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -58,6 +58,7 @@ static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; static TCGv_i32 cpu_softint; #else static TCGv cpu_wim; +static TCGv cpu_asr17; #endif /* local register indexes (only used inside old micro ops) */ static TCGv cpu_tmp0; @@ -2049,6 +2050,8 @@ static void disas_sparc_insn(DisasContext * dc) rs1 = GET_FIELD(insn, 13, 17); switch(rs1) { case 0: /* rdy */ + gen_movl_TN_reg(rd, cpu_y); + break; #ifndef TARGET_SPARC64 case 0x01 ... 0x0e: /* undefined in the SPARCv8 manual, rdy on the microSPARC @@ -2058,6 +2061,11 @@ static void disas_sparc_insn(DisasContext * dc) case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 manual, rdy on the microSPARC II */ + + if (rs1 == 0x11) { /* Read %asr17 */ + gen_movl_TN_reg(rd, cpu_asr17); + break; + } #endif gen_movl_TN_reg(rd, cpu_y); break; @@ -5019,6 +5027,8 @@ void gen_intermediate_code_init(CPUSPARCState *env) #else cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), "wim"); + cpu_asr17 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, asr17), + "asr17"); #endif cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), "cond");